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SST49LF020-33-4C-WH Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST49LF020-33-4C-WH Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
3 / 38 page Advance Information 2 Megabit LPC Flash SST49LF020 3 ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526 ory contents may become invalid due to data being altered had been disrupted from an incomplete Erase or Program operation. Registers There is one register available on the SST49LF020. The General Purpose Inputs Register. This register appears at its respective address location in the 4 GByte system memory map. General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF020. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register appears at FFBC0100H in the 4 GBytes system memory map. See General Purpose Inputs Register table for the GPI_REG bits and function. CE# The CE# pin, enables and disables the SST49LF020, con- trolling read and write access of the device. To enable the SST49LF020, the CE# pin must be driven low one cycle prior to LFRAME# being driven low. For write (erase or pro- gram) cycles, the CE# pin must remain low during the inter- nal programming. When CE# is high, the SST49LF020 is placed in low-power standby-mode. LFRAME# The LFRAME# signifies the start of a frame or the termina- tion of a broken frame. Asserting LFRAME# for one or more clock cycle and driving a valid START value on LAD[3:0] will initiate device operation. The device enters standby mode when LFRAME# and CE# are high and no internal operations is in progress. Abort Mechanism If LFRAME# is driven low for one or more clock cycles dur- ing a LPC cycle, the cycle will be terminated and the device will wait for the ABORT command. The host must drive the LAD[3:0] with ‘1111b’ (ABORT command) to return the device to the ready mode. If abort occurs during the inter- nal write cycle, the data may be incorrectly programmed or erased. It is required to wait for the Write operation to com- plete prior to initiation of the abort command. It is recom- mended to check the write status with Data# Polling (DQ7) or Toggle Bit (DQ6) pins. One other option is to wait for the fixed write time to expire. GENERAL PURPOSE INPUTS REGISTER Bit Function Pin# 32-PLCC 32-TSOP 7:5 Reserved - - 4 GPI[4] Reads status of general purpose input pin 30 7 3 GPI[3] Reads status of general purpose input pin 3 15 2 GPI[2] Reads status of general purpose input pin 416 1 GPI[1] Reads status of general purpose input pin 517 0 GPI[0] Reads status of general purpose input pin 618 |
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