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TPS54110Q1 Datasheet(PDF) 11 Page  Texas Instruments 


TPS54110Q1 Datasheet(HTML) 11 Page  Texas Instruments 
11 / 24 page TPS54110−Q1 SLVS837 − JULY 2008 www.ti.com 11 C6 + 1 2 pR1ƒ INT Since C6 is calculated to be 2900 pF, and the location of the integrator crossover frequency is important in setting the overall loop crossover, adjust the value of R1 so that C6 is a standard value of 2700 pF, using equation 18: R1 + 1 2 pC6ƒ LC The value for R1 is 10.7 K Ω The first zero, fZ1 is located at one half the output filter LC corner frequency, so R3 is calculated from: R3 + 1 pC6ƒ LC The second zero, fZ2 is located at the output filter LC corner frequency, so C8 is calculated from: C8 + 1 2 pR1ƒ LC The first pole, fP1 is located to coincide with output filter ESR zero frequency. This frequency is given by: ƒ ESR0 + 1 2 pR ESR C OUT where RESR is the equivalent series resistance of the output capacitor. In this case, the ESR zero frequency is 35.4 kHz, and R5 is calculated from: R5 + 1 2 pC8 ƒ ESR The final pole is placed at a frequency high enough above the closedloop crossover frequency to avoid causing an excessive phase decrease at the crossover frequency while still providing enough attenuation so that there is little or no gain at the switching frequency. The fP2 pole location for this circuit is set to 4 times the closedloop crossover frequency and the last compensation component value C7 is derived: C7 + 1 8 pR3ƒ CO Finally, calculate the R2 resistor value for the output voltage of 3.3 V using equation 24: R2 + R1 0.891 V OUT –0.891 For this TPS54110 design, use R1 = 10.7 k Ω instead of 10.0 k Ω. R2 is then 3.92 kΩ. Since capacitors are only available in a limited range of standard values, the nearest standard value was chosen for each capacitor. The measured closedloop response for this design is shown in Figure 19. BIAS AND BOOTSTRAP CAPACITORS Every TPS54110 design requires a bootstrap capacitor (C3), and a bias capacitor (C4). The bootstrap capacitor must be between 0.022 µF and 0.1 µF. This design uses 0.047 µF. The bootstrap capacitor is located between the PH pins and BOOT. The bias capacitor is connected between the VBIAS pin and AGND. Recommended values are 0.1 µF to 1.0 µF. This design uses 0.1 µF. Use highquality ceramic capacitors with X7R or X5R grade dielectric for temperature stability. P lace them as close to the device pins as possible. (17) (18) (19) (20) (21) (22) (23) (24) 
