Output Current

Internal Clock

PWM, FCCM

PWM, Skip Mode

No Zero-Crossing for two

PWM cycles, and the

device enters CCM

In Skip mode, the PWM sync to

internal clock after entering CCM

UDG-11279

TPS53313

www.ti.com

SLUSAS8

– DECEMBER 2011

LIGHT LOAD OPERATION

In skip mode, when the load current is less than half of inductor ripple current, the inductor current reaches zero

by the end of OFF-Time. The light load control scheme then turns off the low-side MOSFET when inductor

current reaches zero. Since there is no negative inductor current, the energy delivered to the load per switching

cycle is increased compared to the normal PWM mode operation. The controller then reduces the switching

frequency to maintain the output voltage regulation. The switching loss is reduced and thus efficiency is

improved.

In skip mode, when the load current decreases, the switching frequency also decreases continuously in

discontinuous conduction mode (DCM). When the load current is 0 A, the minimum switching frequency is

supply for high-side gate driver.

Figure 12. TPS53313 Operation Modes in Light and Heavy Load Conditions

FORCED CONTINUOUS CONDUCTION MODE

When choosing FCCM, the TPS53313 is operating in continuous conduction mode in both light and heavy load

condition. In this mode, the switching frequency remains constant over the entire load range which is suitable for

applications need tight control of switching frequency at a cost of lower efficiency at light load.

SOFT-START OPERATION

The soft-start operation reduces the inrush current during the start-up time. A slow rising reference is generated

by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage is less than

600 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 600 mV, a

fixed 600-mV reference voltage is used for the error amplifier. The soft-start time has selectable values of 1 ms,

3 ms and 6 ms.

POWER GOOD

The TPS53313 monitors the output voltage through the FB pin. If the FB voltage is within 117% and 83% of the

reference voltage, the power good signal remains high. If the FB voltage is outside of this range, the PG pin pin

is pulled low by the internal open drain output.

During start up, the power good signal has a 200-

μs delay after the FB voltage falls into the power good range

limit when the soft-start time is set to 1 ms. There is also 10-

μs delay during shut down.

Copyright

© 2011, Texas Instruments Incorporated

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