6

Preliminary Specifications

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

©2001 Silicon Storage Technology, Inc.

S71134-02-000

4/01

381

II. SRAM Operation

TRC

TAA

TCO

TLZ(2)

TOHZ(1)

TOH

THZ(1,2)

Data Valid

381 ILL F03.0

Data Out

OE#

ROMCS#

High-Z

Address

TOE

TOLZ

Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given

device and from device to device.

TABLE

Symbol

Parameter

SST30VR041-70

SST30VR041/043-150

Units

Min

Max

Min

Max

Read Cycle Time

70

150

ns

Address Access Time

70

150

ns

Chip Select to Output

70

150

ns

Chip Select to Low-Z Output

0

0

ns

Chip Disable to High-Z Output

25

30

ns

Output Hold from Address Change

10

15

ns

T6.2 381

TABLE

Symbol

Parameter

SST30VR041-70

SST30VR041/043-150

Units

Min

Max

Min

Max

Write Cycle Time

70

150

ns

Chip Select to End-of-Write

60

120

ns

Address Valid to End-of-Write

60

120

ns

Address Set-up Time

0

0

ns

Write Pulse Width

60

120

ns

Write Recovery Time

0

0

ns

Write to Output High-Z

30

60

ns

Data to Write Time Overlap

30

60

ns

Data Hold from Write Time

0

0

ns

End Write to Output Low-Z

0

10

ns

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