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TPIC82010FFER Datasheet(PDF) 27 Page - Texas Instruments |
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TPIC82010FFER Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 92 page  TPIC82000 Series www.ti.com SLDS189 – MAY 2012 3.2.6.4 EEPROM Control ESFR ■M EEprom Write Address Register Not Bit Addressable ESFR: 0xF9 EEpromCONT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 – EEpromWrite EEpromWRadd<5:0> Access – w w w w w w W At Power on reset x 0 1 1 1 1 1 1 At Timer reset x 0 1 1 1 1 1 1 EEpromWrite ON: (1), OFF: (0) EEpromWRadd<5:0> EEprom Write address ■M EEprom DATA Register Not Bit Addressable ESFR: 0xA3 EEpromData BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 – EEpromData<6:0> Access – w w w w w w w At Power on reset x 0 0 0 0 0 0 0 At Timer reset x 0 0 0 0 0 0 0 EEpromData<6:0> EEprom DATA Note: This Register is common to RFdetThres<7:0> ■M EEprom DATA Register Not Bit Addressable ESFR: 0xA3 EEpromData BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Testout EEpromData<6:0> Access r r r r r r r r At Power on reset 0 U U U U U U U At Timer reset 0 S S S S S S S Testout Test output EEpromData<6:0> EEprom DATA Note: This Register is common to RFdetThres<7:0> ■M Test Mode Control Not Bit Addressable ESFR: 0x91 TESTvector BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 – – TestVector<5:0> Access w w w w w w w w At Power on reset 0 0 0 0 0 0 0 0 At Timer reset 0 0 0 0 0 0 0 0 TestVector<5:0> Test Vector Setting; M TestVector<5:0> = 0x3B; Enable to Write access of the EEprom (Upper address: 0x10 to 0x27) ■M RF Detector Control Not Bit Addressable ESFR: 0xA2 RFdetCONT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RFdetPower – – – – – – – Access w w w – – – – w At Power on reset 0 0 0 x x x x U At Timer reset U U U x x x x U RFdetPower Note: This bit is consolidated with RF Detector Power EEPROM Bias Power Control Control. M1 = Power On, 0 = Power Off Copyright © 2012, Texas Instruments Incorporated FUNCTION DESCRIPTION 27 Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series |
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