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TPIC82000FFER Datasheet(PDF) 82 Page - Texas Instruments |
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TPIC82000FFER Datasheet(HTML) 82 Page - Texas Instruments |
82 / 92 page TPIC82000 Series SLDS189 – MAY 2012 www.ti.com 3.8 Debug Mode 3.8.1 ESFR ■M TEST Mode control0 Not Bit Addressable ESFR: 0x84 TESTmux0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EN UART Reserved EN_Interrupt EN BP Interrupt Reserved Access w w w w w w w w At Power on reset 0 0 0 0 0 0 0 0 At Timer reset 0 0 0 0 0 0 0 0 EN UART Enable UART debug interface EN_Interrupt Interrupt IE0 from RESET_TEST 0: Disable, 1: Enable EN BP Interrupt Interrupt IE0 from RESET TEST 0: Disable, 1: Enable ■M TEST Mode Control Not Bit Addressable ESFR: 0x91 TESTvector BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Reserved TestVector<5:0> Access w w w w w w w w At Power on reset 0 0 0 0 0 0 0 0 At Timer reset 0 0 0 0 0 0 0 0 TestVector<5:0> To be used as a TEST Vector when Micro restarts ■M Upper Breakpoint Register Not Bit Addressable ESFR: 0x92 BPU BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 – – BPU<5:0> Access – – w w w w w w At Power on reset x x 0 0 0 0 0 0 At Timer reset x x 0 0 0 0 0 0 ■M Lower Breakpoint Register Not Bit Addressable ESFR: 0x93 BPL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BPL<7:0> Access w w w w w w w w At Power on reset 0 0 0 0 0 0 0 0 At Timer reset 0 0 0 0 0 0 0 0 BPU<5:0> Upper Breakpoint Register BPL<7:0> Lower Breakpoint Register BreakPoint Address BP<13:0> = BPU<5:0> * 256 + BPL<7:0> 82 FUNCTION DESCRIPTION Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series |
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