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TNETX3110PGV Datasheet(PDF) 8 Page - Texas Instruments |
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TNETX3110PGV Datasheet(HTML) 8 Page - Texas Instruments |
8 / 65 page TNETX3110 ThunderSWITCH ™ 8/3 ETHERNET™ SWITCH WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS047A – MARCH 1998 – REVISED APRIL 1999 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (ports 08–10) (continued) TERMINAL I/O INTERNAL DESCRIPTION† NAME NO. I/O RESISTOR DESCRIPTION† M08TXD3 M08TXD2 M08TXD1 M08TXD0 M09TXD3 M09TXD2 M09TXD1 M09TXD0 M10TXD3 M10TXD2 M10TXD1 M10TXD0 38 37 36 35 61 60 59 57 86 85 84 83 O None Transmit data (nibble transmit data). When MxxTXEN is asserted, these signals carry transmit data. Data on these signals is synchronous to MxxTCLK. MxxTXD0 is the least significant bit and MxxTXD3 is the most significant bit. M08TXEN M09TXEN M10TXEN 39 62 87 O None Transmit enable. MxxTXEN indicates valid transmit data on MxxTXD3–MxxTXD0. M08TXER M09TXER M10TXER 41 63 89 O None Transmit error. MxxTXER allows coding errors to be propagated across the MII. MxxTXER is taken high when an under-run in the transmit FIFO for port xx occurs and causes fill data to be transmitted (MxxTXER is low otherwise). MxxTXER is asserted at the end of an under-running frame, enabling the device to force a coding error. † xx = ports 08, 09, and 10 |
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