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M378B5773DH0 Datasheet(PDF) 16 Page - Samsung semiconductor |
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M378B5773DH0 Datasheet(HTML) 16 Page - Samsung semiconductor |
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16 / 41 page  - 16 - datasheet DDR3 SDRAM Rev. 1.4 Unbuffered DIMM 12.2 VREF Tolerances. The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Fur- thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 2. This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. voltage VDD VSS time |
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