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MFRC630 Datasheet(PDF) 61 Page - NXP Semiconductors |
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MFRC630 Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 118 page  MFRC630 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 6 September 2012 227531 61 of 118 NXP Semiconductors MFRC630 Contactless reader IC 9.5.1 IRQ0 register Interrupt request register 0. 9.5.2 IRQ1 register Interrupt request register 1. Table 51. IRQ0 register (address 06h); reset value: 00h Bit 7 6 5 4 3 2 1 0 Symbol Set Hi AlertIrq Lo AlertIrq IdleIrq TxIrq RxIrq ErrIrq RxSOF Irq Access rights wdy dy dy dy dy dy dy Table 52. IRQ0 bits Bit Symbol Description 7 Set 1: writing a 1 to a bit position 6..0 sets the interrupt request 0: Writing a 1 to a bit position 6..0 clears the interrupt request 6 HiAlerIrq Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIrq stores this event and can only be reset if Set is cleared. 5 LoAlertIrq Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert, LoAlertIrq stores this event and can only be reset if Set is cleared 4 IdleIrq Set, when a command terminates by itself e.g. when the Command changes its value from any command to the Idle command. If an unknown command is started, the Command changes its content to the idle state and the bit IdleIRq is set. Starting the Idle command by the Controller does not set bit IdleIRq. 3 TxIrq Set, when data transmission is completed, which is immediately after the last bit is sent. 2 RxIrq Set, when the receiver detects the end of a data stream. Note: This flag is no indication that the received data stream is correct. The error flags have to be evaluated to get the status of the reception. 1 ErrIrq Set, when the one of the following errors is set: FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr 0 RxSOFlrq Set, when a SOF or a subcarrier is detected Table 53. IRQ1 register (address 07h) Bit 7 6 5 4 3 2 1 0 Symbol Set GlobalIrq LPCD_Irq Timer4Irq Timer3Irq Timer2Irq Timer1Irq Timer0Irq Access rights wdy dy dy dy dy dy dy |
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