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1

3

16

X

X

X

D15

D14

D13

D12

D1

X

SCLK

DIN

X

D15

(1)

D14

(1)

D13

(1)

D12

(1)

D1

(1)

X

DOUT

X

t

wH

t

wL

t

su(D)

t

h(D)

FS

( CMode)

m

FS

(DSPMode)

t

wH(FS)

t

wL(FS)

t

su(FS

CK)

-

t

su(C16

FS)

-

D0

D0

(1)

17

t

su(FS

C17)

-

t

su(CK

FS)

-

NOTE:(1)Previousinputdata.

2

4

LDAC

OUTx

±0.5LSB

DIGITAL INPUT TIMING REQUIREMENTS

TLV5610IYZ

SBAS389A – JULY 2006 – REVISED JULY 2006

Figure 1. Serial Interface Timing

Figure 2. Output Timing

PARAMETER

MIN

TYP

MAX

UNIT

Setup time, FS low before next negative SCLK edge

8

ns

Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising edge

10

ns

of FS. µC mode only

µC mode, setup time, FS high before 17th positive SCLK.

10

ns

DSP mode, setup time, SLCK low before FS low.

5

ns

LDAC duration low

10

ns

SCLK pulse duration high

16

ns

SCLK pulse duration low

16

ns

Setup time, data ready before SCLK falling edge

8

ns

Hold time, data held valid after SCLK falling edge

5

ns

FS duration high

10

ns

FS duration low

10

ns

See Analog Output Dynamic

Settling time

Performance

4

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