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TLV5610IYZ Datasheet(PDF) 11 Page - Texas Instruments

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Part No. TLV5610IYZ
Description  DIGITAL-TO-ANALOG CONVERTER in a Wafer Chip-Scale Package—Pb-Free/Green
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLV5610IYZ Datasheet(HTML) 11 Page - Texas Instruments

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USING THE TLV5610IYZ WAFER CHIP-SCALE PACKAGE (WCSP)
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TLV5610IYZ
SBAS389A – JULY 2006 – REVISED JULY 2006
TLV5610 qualifications are done using a wire-bonded small outline (SO) package. The qualifications include:
steady state life, thermal shock, ESD, latch-up, biased HAST, autoclave, and characterization. These qualified
devices are orderable as TLV5610IDW.
NOTE: The wafer chip-scale package (WCSP) for the TLV5610IYZ uses the same die as TLV5610IDW, but is
not qualified. WCSP qualification, including board level reliability (BLR), is the responsibility of the customer.
It is recommended that underfill be used for increased reliability. BLR is application-dependent, but may include
tests such as: temperature cycling, drop test, key push, bend, vibration, and package shear.
For general guidelines on board assembly of the WCSP, the following documentation provides more details:
Application Report NanoStar™ & NanoFree™ 300
µm Solder Bump WCSP Application—SBVA017
Design Summary WCSP Little Logic—SCET007B
NOTE: The use of underfill is required and greatly reduces the risk of thermal mismatch fails.
Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board
level/system level reliability. The process is to dispense the epoxy under the dice after die attach reflow. The
epoxy adheres to the body of the device and to the printed-circuit board. It reduces stress placed upon the
solder joints because of thermal coefficient of expansion (TCE) mismatch between the board and the
component. Underfill material is highly filled with silica or other fillers to increase epoxy modulus, reduce creep
sensitivity, and decrease material TCE.
NOTE: The recommendation for peak flow temperatures of +250
°C to +260°C is based on general empirical
results that indicate that this temperature range is needed to facilitate good wetting of the solder bump to the
substrate or circuit board pad. Lower peak temperatures may cause nonwets (cold solder joints).
A.
All linear dimensions are in millimeters.
B.
This drawing is subject to change without notice.
Figure 10. TLV5610IYZ Wafer Chip-Scale Package
11
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