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Test Point Descriptions

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Test Point Descriptions

Fourteen wire-loop test points have been provided as convenient connection points for digital voltmeters

(DVM) or oscilloscope probes to aid in the evaluation of the IPS device. A via labled PH is available near

U1 to scope on the switching frequency. A description of each test point is listed in Table 3

Table 3. Test Point Descriptions

TEST POINT

DESCRIPTION

VIN

Input voltage monitor. Connect DVM to this point for measuring efficiency.

VOUT

Output voltage monitor. Connect DVM to this point for measuring efficiency, line regulation, and

load regulation.

GND

Input and output voltage monitor grounds (located between terminal blocks). Reference the above

DVMs to any of these four ground points.

VIN (scope)

Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple

voltage.

VOUT (scope)

Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output

ripple voltage and transient response.

PWRGD

Monitors the power good signal of the IPS device. This is an open drain signal that requires an

external pull-up resistor to V

recommended. PWRGD is high if the output voltage is within 92% to 106% of its nominal value.

INH/UVLO

Connect this point to control ground to inhibit the IPS device. Allow this point to float to enable the

device. Do not use a pull-up resistor. An external resistor can be connected from this point to

control ground to increase the under-voltage lockout (UVLO) of the device.

RT/CLK

Connects to the RT/CLK pin of the IPS device. An external clock signal can be applied to this

point to synchronize the device to an appropriate frequency.

SS/TR

Connects to the internal slow-start capacitor of the IPS device. An external capacitor can be

connected from this point to control ground to increase the slow-start time of the device. This

point can also be used as an input for tracking applications.

GND

Control grounds (located along bottom of EVM). Reference any signals associated with the

control test points to either of these two ground points.

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Operation Notes

The UVLO threshold of the factory-stock EVM is approximately 3.05 V with 0.3 V of hysteresis. The input

voltage must be above the UVLO threshold in order to startup the IPS device. The UVLO threshold can be

increased by adding a resistor to the INH/UVLO test point as described above. After startup, the minimum

input voltage to the IPS device must be at least 2.95 V or (V

produce a regulated output. The maximum operating input voltage for the IPS device is 6 V. Refer to the

TPS84410 datasheet for further information on the input voltage range and UVLO operation.

After application of the proper input voltage, the output voltage of the IPS device will ramp to its final value

in approximately 1 ms. If desired, this soft-start time can be increased by adding a capacitor to the SS/TR

test point as described above. Refer to the TPS84410 datasheet for further information on adjusting the

soft-start time.

Table 1 lists the recommended switching frequencies for each of the V

recommendations cover operation over a wide range of input voltage and output load conditions. Several

factors such as duty cycle, minimum on-time, minimum off-time, and current limit influence selection of the

appropriate switching frequency. In some applications, other switching frequencies might be used for

particular output voltages, depending on the above factors. Refer to the TPS84410 datasheet for further

information on switching frequency selection, including synchronization.

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SLUU633A

– September 2011 – Revised February 2012

TPS84410EVM-001/TPS84210EVM-002/TPS84610EVM-003, 2-A to 6-A

Integrated Power Solution

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