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CSD17303Q5 Datasheet(PDF) 2 Page - Texas Instruments |
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CSD17303Q5 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page www.ti.com 1 TPS51916EVM-746 Schematic ........................................................................................... 5 2 Tip and Barrel Measurement for VDDQ Output Ripple ................................................................ 6 3 TPS51916EVM-746 Recommended Test Setup ....................................................................... 7 4 DDR3 VDDQ Efficiency .................................................................................................... 9 5 DDR3 VDDQ Load Regulation .......................................................................................... 10 6 DDR3 VDDQ Line Regulation ........................................................................................... 10 7 DDR3 VTT Load Regulation ............................................................................................. 11 8 DDR3 VTTREF Load Regulation ........................................................................................ 11 9 DDR3 VTT Dropout Voltage ............................................................................................. 12 10 DDR3 S5 Enable Turnon ................................................................................................. 12 11 DDR3 S5 Enable Turnoff ................................................................................................. 12 12 DDR3 S5 Enable Turnon With 1-V Prebias at VDDQ ................................................................ 13 13 DDR3 S3 Enable Turnon ................................................................................................. 13 14 DDR3 S3 Enable Turnoff ................................................................................................. 13 15 DDR3 VDDQ Output Ripple ............................................................................................. 14 16 DDR3 VDDQ Switching Node ........................................................................................... 14 17 VDDQ Output Transient From DCM to CCM ......................................................................... 15 18 VDDQ Output Transient From CCM to DCM ......................................................................... 15 19 DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current .................................................... 15 20 Top Board at 12 Vin, 1.5 VDDQ/20 A, No Load at VTT, 25 °C Ambient Without Airflow ........................ 16 21 DDR3 VDDQ Bode Plot at 12 Vin, 1.5 VDDQ/10 A ................................................................... 16 22 DDR3 VTT Bode Plot at 12 Vin, 1.5 VDDQ/0 A and VTT 1-A Sourcing ........................................... 17 23 TPS51916EVM-746 Top Layer Assembly Drawing ................................................................... 17 24 TPS51916EVM-746 Bottom Assembly Drawing ...................................................................... 18 25 TPS51916EVM-746 Top Copper ....................................................................................... 18 26 TPS51916EVM-746 Layer-2 Copper ................................................................................... 19 27 TPS51916EVM-746 Layer-3 Copper ................................................................................... 19 28 TPS51916EVM-746 Bottom Copper ................................................................................... 20 List of Tables 1 TPS51916EVM-746 Electrical Performance Specifications ........................................................... 3 2 S3, S5 Enable Selection ................................................................................................... 8 3 Test Point Functions ........................................................................................................ 8 4 TPS51916EVM-746 Bill of Materials .................................................................................... 21 2 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 SLUU526 – August 2011 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Reference |
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