xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

[1]

an "*" in the Access column means that this register is subject to control access conditions in Write mode.

0826

Cfg_7_CS_N

R/W*

0

CS[0]

0

0

N[3:0]

0100 0100

0827

Cfg_8_Np

R/W

0

0

0

NP[4:0]

0000 1111

0828

Cfg_9_S

R/W*

0

0

0

0

0

0

0

S

0000 0000

0829

Cfg_10_HD_CF

R/W*

HD

0

0

0

0

0

CF[1:0]

0000 0000

082C

Cfg_01_2_LID

R/W*

0

0

0

LID[4:0]

0001 1011

082D

Cfg_02_2_LID

R/W*

0

0

0

LID[4:0]

0001 1100

084C

Cfg01_13_FCHK R

FCHK[7:0]

0000 0000

084D

Cfg02_13_FCHK R

FCHK[7:0]

0000 0000

0870

Lane0_0_Ctrl

R/W

0

SCR_IN_

MODE

LANE_MODE[1:0]

0

LANE_

POL

LANE_CLK_

POS_EDGE

LANE_PD

0000 0001

0871

Lane1_0_Ctrl

R/W

0

SCR_IN_

MODE

LANE_MODE[1:0]

0

LANE_

POL

LANE_CLK_

POS_EDGE

LANE_PD

0000 0000

0890

ADCA_0_Ctrl

R/W

0

0

ADC_MODE[1:0]

0

0

0

ADC_PD

0000 0001

0891

ADCB_0_Ctrl

R/W

0

0

ADC_MODE[1:0]

0

0

0

ADC_PD

0000 0000

Table 17.

Address

(hex)

Register name

Bit definition

Default

(bin)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0