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ADC1213S Datasheet(PDF) 20 Page - Integrated Device Technology

Part # ADC1213S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ADC1213S Datasheet(HTML) 20 Page - Integrated Device Technology

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ADC1213S_SER 3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
20 of 37
Integrated Device Technology
ADC1213S series
Single 12-bit ADC; serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.3.4 Clock input divider
The ADC1213S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
The output should be terminated when 100
 (typical) is reached at the receiver side.
Table 12.
Duty cycle stabilizer
bit DCS_EN
Description
0
duty cycle stabilizer disable
1
duty cycle stabilizer enable
Fig 19. CML output connection to the receiver (DC-coupling)
VDDD
VDDD
CMLP
CMLN
AGND
005aaa197
12 mA to 26 mA
100 Ω
+
RECEIVER
50 Ω
50 Ω
-


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