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ADC1005S060TS Datasheet(PDF) 9 Page - Integrated Device Technology |
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ADC1005S060TS Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 18 page ADC1005S060_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 9 of 18 Integrated Device Technology ADC1005S060 Single 10 bits ADC, up to 60 MHz [1] The rise and fall times of the clock signal must not be less than 0.5 ns. [2] The input admittance is Yi 1 Ri ----- j C i ++ [3] Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 C. b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 C. [4] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. a) The current flowing into the resistor ladder is I VRT VRB – ROB RL ROT ++ --------------------------------------- = and the full-scale input range at the converter, to cover code 0 to 1023 is VI RL IL RL ROB RL ROT ++ --------------------------------------- VRT VRB + 0.8375 VRT VRB – == = b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio RL ROB RL ROT ++ --------------------------------------- will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [5] EG V1023 V0 – V ip p – – Vip p – ------------------------------------------------------- 100 = [6] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. [7] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. [8] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: S/N = ENOB 6.02 + 1.76 dB. [9] Intermodulation measured relative to either tone with analog input frequencies of 4.3 MHz and 4.5 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. [10] Output data acquisition: the output data is available after the maximum delay time of td(o). IDT recommends the lowest possible output load. These parameters are guaranteed by characterization and not by production test. CL load capacitance - - 10 pF SR slew rate VCCO = 2.7 V 0.2 0.3 - V/ns 3-state output delay times (fclk = 60 MHz; VCCO = 3.3 V); see Figure 5 tdZH float to active HIGH delay time - 16 20 ns tdZL float to active LOW delay time - 30 34 ns tdHZ active HIGH to float delay time - 25 30 ns tdLZ active LOW to float delay time - 23 27 ns Table 6. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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