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SN65LVDS051PWRG4Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVDS051PWRG4Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 27 page  SN65LVDS179-Q1, SN65LVDS180-Q1 SN65LVDS050-Q1, SN65LVDS051-Q1 www.ti.com SGLS204B – SEPTEMBER 2003 – REVISED NOVEMBER 2011 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT+ Positive-going differential input voltage threshold 50 See Figure 5 and mV VIT- Negative-going differential input voltage threshold –50 IOH = -8 mA 2.4 VOH High-level output voltage V IOH = -4 mA 2.8 VOL Low-level output voltage IOL = 8 mA 0.4 V VI = 0 –2 –11 –20 II Input current (A or B inputs) μA VI = 2.4 V –1.2 –3 II(OFF) Power-off input current (A or B inputs) VCC = 0 ±20 μA IIH High-level input current (enables) VIH = 5 V ±10 μA IIL Low-level input current (enables) VIL = 0.8 V ±10 μA IOZ High-impedance output current VO = 0 or 5 V ±10 μA CI Input capacitance 5 pF (1) All typical values are at 25 °C and with a 3.3-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.7 2.7 ns tPHL Propagation delay time, high-to-low-level output 1.7 2.7 ns RL = 100 Ω, tr Differential output signal rise time 0.8 1 ns CL = 10 pF, tf Differential output signal fall time 0.8 1 ns See Figure 2 tsk(p) Pulse skew (|tpHL - tpLH|) (2) 300 ps tsk(o) Channel-to-channel output skew(3) 150 ps ten Enable time 4.3 10 ns See Figure 4 tdis Disable time 3.1 10 ns (1) All typical values are at 25 °C and with a 3.3-V supply. (2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. (3) tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 3.7 4.5 ns tPHL Propagation delay time, high-to-low-level output 3.7 4.5 ns CL = 10 pF, tsk(p) Pulse skew (|tpHL - tpLH|) (2) 0.3 ns See Figure 6 tr Output signal rise time 0.7 1.5 ns tf Output signal fall time 0.9 1.5 ns tPZH Propagation delay time, high-impedance-to-high-level output 2.5 ns tPZL Propagation delay time, high-impedance-to-low-level output 2.5 ns See Figure 7 tPHZ Propagation delay time, high-level-to-high-impedance output 7 ns tPLZ Propagation delay time, low-level-to-high-impedance output 4 ns (1) All typical values are at 25 °C and with a 3.3-V supply. (2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Copyright © 2003–2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SN65LVDS179-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 |
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