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SWITCHING CHARACTERISTICS

PARAMETER MEASUREMENT INFORMATION

_

+

A

GC

EN

Q

Z

Y

D.U.T.

GND

2

4

5

1

3

6

7

8

9

50 W

50 W

S1

_

+

+

−

+

−

+

−

+

−

+

−

_

+

_

+

SN65LVDS18, SN65LVP18

SN65LVDS19, SN65LVP19

SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

A to Q

340

460

See Figure 4

ps

D to Y or Z

460

630

20

80

ps

130

LVDS, See Figure 4

140

250

20%-to-80% differential signal rise time

ps

LVPECL, See Figure 4

190

300

LVDS, See Figure 4

140

250

20%-to-80% differential signal fall time

ps

LVPECL, See Figure 4

210

300

2

4

2-GHz 50%-duty-cycle square-wave input,

ps

See Figure 5

17

24

Intrinsic phase jitter

1 GHz

0.12

ps

Propagation delay time,

30

high-level-to-high-impedance output

Propagation delay time,

30

low-level-to-high-impedance output

See Figure 6

ns

Propagation delay time,

30

high-impedance-to-high-level output

Propagation delay time,

30

high-impedance-to-low-level output

(1)

(2)

Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when

both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(3)

Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.

(4)

Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle

pairs.

(1)

(2)

S1 is open for the SN65LVDS18 and closed for the SN65LVP18.

Figure 1. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP18

4