SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1

SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1

www.ti.com

SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Driver Switching Characteristics

Propagation delay time,

7.1

STB / S at 0 V, See Figure 7

65

ns

low-to-high level output

Propagation delay time,

7.2

STB / S at 0 V, See Figure 7

50

ns

high-to-low level output

7.3

Differential output signal rise time

STB / S at 0 V, See Figure 7

25

ns

7.4

Differential output signal fall time

STB / S at 0 V, See Figure 7

55

ns

Enable time from standby or silent

7.5

See Figure 10

20

µs

mode to normal mode dominant

7.6

(4)

Dominant time out

See Figure 13

300

400

700

µs

Receiver Electrical Characteristics

Positive-going input threshold

8.1

STB / S at 0 V, See Table 5

800

900

mV

voltage, normal mode

Negative-going input threshold

8.2

STB / S at 0 V, See Table 5

500

650

mV

voltage, normal mode

8.3

100

125

mV

Input threshold voltage,

8.4

standby mode (SN65HVDA541

400

1150

mV

only)

Power-off (unpowered) bus input

8.5

3

µA

leakage current

Input capacitance to ground

3.3 V.

8.6

13

pF

(CANH or CANL)

3.3 V.

8.7

Differential input capacitance

5

pF

8.8

Differential input resistance

29

80

k

Ω

3.3 V, STB at 0 V

8.9

Input resistance (CANH or CANL)

14.5

25

40

k

Ω

STB at 0 V

Input resistance matching

8.10

–3

0

3

%

Receiver Switching Characteristics

Propagation delay time,

9.1

STB / S at 0 V , See Figure 9

95

ns

low-to-high-level output

Propagation delay time,

9.2

STB / S at 0 V , See Figure 9

60

ns

high-to-low-level output

9.3

Output signal rise time

STB / S at 0 V , See Figure 9

13

ns

9.4

Output signal fall time

STB / S at 0 V , See Figure 9

10

ns

Dominant time required on bus for

9.5

wake-up from standby

1.5

5

µs

(SN65HVDA541 only)

Recessive time on the bus to clear

Figure 4

the standby mode receiver output

9.6

(RXD) if standby mode is entered

1.5

5

µs

while bus is dominant

(SN65HVDA541 only)

(4)

releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant

again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the

minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,

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