SN65HVDA1040A-Q1

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SLLS995C

– FEBRUARY 2010 – REVISED FEBRUARY 2011

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions including operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Driver Switching Characteristics

7.1

Propagation delay time, low-to-high level output

STB at 0 V, See Figure 7

25

65

120

ns

7.2

Propagation delay time, high-to-low level output

STB at 0 V, See Figure 7

25

45

120

ns

7.3

Differential output signal rise time

STB at 0 V, See Figure 7

25

ns

7.4

Differential output signal fall time

STB at 0 V, See Figure 7

45

ns

Enable time from standby mode to normal mode

7.5

See Figure 10

10

µs

and transmission of dominant

7.6

300

450

700

µs

Receiver

Positive-going input threshold voltage, high-speed

8.1

STB at 0 V, See Table 4

800

900

mV

mode

Negative-going input threshold voltage,

8.2

STB at 0 V, See Table 4

500

650

mV

high-speed mode

8.3

100

125

mV

8.4

Input threshold voltage, standby mode

500

1150

mV

8.5

High-level output voltage

4

4.6

V

8.6

Low-level output voltage

0.2

0.4

V

Power-off bus input current (unpowered bus

CANH = CANL = 5 V,

8.7

3

µA

leakage current)

8.8

Power-off RXD leakage current

20

µA

TXD at 3 V,

8.9

Input capacitance to ground (CANH or CANL)

13

pF

8.10

Differential input capacitance

6

pF

8.11

Differential input resistance

TXD at 3 V, STB at 0 V

30

80

k

Ω

8.12

Input resistance (CANH or CANL)

TXD at 3 V, STB at 0 V

15

30

40

k

Ω

Input resistance matching

8.13

–3

0

3

%

[1

Receiver Switching Characteristics

9.1

Propagation delay time, low-to-high-level output

STB at 0 V , See Figure 9

60

90

130

ns

9.2

Propagation delay time, high-to-low-level output

STB at 0 V , See Figure 9

45

70

130

ns

9.3

Output signal rise time

STB at 0 V , See Figure 9

8

ns

9.4

Output signal fall time

STB at 0 V , See Figure 9

8

ns

Dominant time required on bus for wake-up from

9.5

1.5

5

µs

standby

STB Pin

10.1

High-level input voltage, STB input

2

V

10.2

Low-level input voltage, STB input

0.8

V

10.3

High-level input current

STB at 2 V

–10

0

µA

10.4

Low-level input current

STB at 0.8 V

–10

0

µA

SPLIT Pin

11.1

Output voltage

V

11.2

Leakage current, standby mode

STB at 2 V,

–5

5

µA

(2)

releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant

again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the

minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,

bit rate. The minimum bit rate may be calculated by:

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