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SM320C50GFAM66 Datasheet(PDF) 8 Page - Texas Instruments |
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SM320C50GFAM66 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 37 page SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME TYPE† DESCRIPTION OSCILLATOR/TIMER SIGNALS (CONTINUED) CLKMD1 CLKMD2 I CLKMD1 CLKMD2 Clock mode 0 0 External clock with divide-by-two option. Input clock is provided to X2/CLKIN1. Internal oscillator and PLL are disabled. 0 1 Reserved for test purposes 1 0 External divide-by-one option. Input clock is provided to CLKIN2. Internal oscillator is disabled and internal PLL is enabled. 1 1 Internal or external divide-by-two option. Input clock is provided to X2/CLKIN1. Internal oscillator is enabled and internal PLL is disabled. X2/CLKIN I Input to the internal oscillator from the crystal. If the internal oscillator is not being used, a clock can be input to the device on X2/CLKIN. The internal machine cycle is half this clock rate. X1 O Output from the internal oscillator for the crystal. If the internal oscillator is not used, X1 must be left unconnected. This signal does not go to the high-impedance state when OFF is active (low). CLKIN2 I Divide-by-one input clock for driving the internal machine rate. TOUT O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1 cycle wide. SUPPLY PINS VDD1 VDD2 VDD3 VDD4 I Power supply for data bus VDD5 VDD6 I Power supply for address bus VDD7 VDD8 I Power supply for inputs and internal logic VDD9 VDD10 I Power supply for address bus VDD11 VDD12 I Power supply for memory control signals VDD13 VDD14 I Power supply for inputs and internal logic VDD15 VDD16 I Power supply for memory control signals VSS1 VSS2 I Ground for memory control signals VSS3 VSS4 VSS5 VSS6 I Ground for data bus VSS7 VSS8 VSS9 VSS10 I Ground for address bus VSS11 VSS12 I Ground for memory control signals VSS13 VSS14 VSS15 VSS16 I Ground for inputs and internal logic † I = Input, O = Output, Z = High-Impedance |
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