Lattice Semiconductor Corporation

(1.31, 30-MAR-2012)

www.latticesemi.com/

6

AC Timing Guidelines

The following examples provide some guidelines of device performance. The actual performance depends on the

specific application and how it is physically implemented in the iCE65P FPGA using the Lattice iCEcube2 software.

The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply

derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes.

Programmable Logic Block (PLB) Timing

Table 8 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths

shown in Figure 5 and Figure 6.

Figure 5 PLB Sequential Timing Circuit

Logic Cell

PAD

PIO

PAD

PIO

GBIN

GBUF

LUT4

D

Q

DFF

Logic Cell

Figure 6 PLB Combinational Timing Circuit

LUT4

PAD

PIO

PAD

PIO

Logic Cell

Table 8: Typical Programmable Logic Block (PLB) Timing

Nominal VCC

1.2 V

units

Description

Typ.

Sequential Logic Paths

GBIN

input

GBIN

input

Flip-flop toggle frequency. DFF flip-flop output fed back to LUT4 input with

4-input XOR, clocked on same clock edge

256

MHz

DFF

clock

input

PIO

output

Logic cell flip-flop (DFF) clock-to-output time, measured from the DFF CLK

input to PIO output, including interconnect delay.

3.9

ns

GBIN

input

DFF

clock

input

Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network

to clock input on the logic cell DFF flip-flop.

1.5

ns

PIO

input

GBIN

input

Minimum setup time on PIO input, through LUT4, to DFF flip-flop D-input

before active clock edge on the GBIN input, including interconnect delay.

.67

ns

GBIN

input

PIO

input

Minimum hold time on PIO input, through LUT4, to DFF flip-flop D-input

after active clock edge on the GBIN input, including interconnect delay.

0

ns

Combinational Logic Paths

PIO

input

LUT4

input

Asynchronous delay from PIO input pad to adjacent PLB interconnect.

1.8

ns

LUT4

input

LUT4

output

Logic cell LUT4 combinational logic propagation delay, regardless of logic

complexity from input to output.

0.34

ns

LUT4

output

PIO

output

Asynchronous delay from adjacent PLB interconnect to PIO output

pad.

3.7

ns