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FSL206MRL Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FSL206MRL Datasheet(HTML) 9 Page - Fairchild Semiconductor |
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9 / 14 page  © 2011 Fairchild Semiconductor Corporation FSL206MR • Rev. 1.0.5 www.fairchildsemi.com Functional Description Startup At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (CA) connected to the VCC pin, as illustrated in Figure 15. An internal high-voltage regulator (HV REG) located between the VSTR and VCC pins regulates the VCC to 7.8V and supplies operating current. Therefore, FSL206MR needs no auxiliary bias winding. VREF UVLO HV/REG 7.8V 2 VSTR 3 VCC CA VDC,link ICH ISTART Figure 15. Startup Block Oscillator Block The oscillator frequency is set internally and the FPS™ has a random frequency fluctuation function. Fluctuation of the switching frequency can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the range of the frequency variation. The range of frequency variation is fixed internally; however, its selection is randomly chosen by the combination of an external feedback voltage and internal free-running oscillator. This randomly chosen switching frequency effectively spreads the EMI noise near switching frequency and allows the use of a cost-effective inductor instead of an AC input line filter to satisfy world-wide EMI requirements. Figure 16. Frequency Fluctuation Waveform Feedback Control FSL206MR employs Current-Mode control, as shown in Figure 17. An opto-coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. When the shunt regulator reference pin voltage exceeds the internal reference voltage of 2.5V; the opto- coupler LED current increases, feedback voltage VFB is pulled down, and the duty cycle is reduced. This typically occurs when input voltage is increased or output load is decreased. Figure 17. Pulse-Width-Modulation (PWM) Circuit Leading-Edge Blanking (LEB) At the instant the internal SenseFET is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically cause a high-current spike through the SenseFET. Excessive voltage across the RSENSE resistor leads to incorrect feedback operation in the Current-Mode PWM control. To counter this effect, the FPS employs a leading-edge blanking (LEB) circuit (see Figure 17). This circuit inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on. Protection Circuits The protective functions include Overload Protection (OLP), Over-Voltage Protection (OVP), Under-Voltage Lockout (UVLO), Line Under-Voltage Protection (LUVP), Abnormal Over-Current Protection (AOCP), and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the SenseFET remains off. This causes VCC to fall. When VCC reaches the UVLO stop voltage VSTOP (7V), the protection is reset and the internal high- voltage current source charges the VCC capacitor via the VSTR pin. When VCC reaches the UVLO start voltage VSTART (8V), the FPS resumes normal operation. In this manner, auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. |
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