-W

-W

e

1A

1B

EQ

EQ

1Y

1Z

P11

P12

2

1DE

S1

0

1

2A

2B

EQ

EQ

S2

0

1

2Y

2Z

2

P21

P22

2DE

V

BB

R

T

R

T

V

BB

R

T

R

T

2x1

MUX

2x1

MUX

SN65LVCP202

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

LOGIC DIAGRAM

TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

High Speed I/O

Differential Inputs (with 50-

Ω

xA

2, 5

Line-side differential inputs, CML compatible

xB

3, 6

xA = P; xB = N

xY

17, 14

Differential output xY = P; xZ = N

Switch-side differential outputs, VML

xZ

16, 13

Control Signals

Data enable; active-low; LVTTL; when not enabled, the output

xDE

24, 7

Input

is in high-impedance state for power savings.

S1, S2

1, 18

Input; S1 = channel 1

Switching selection; LVTTL

P11–P22

22, 21, 9, 10

Input; P11 = channel 1 bit 1

Output preemphasis control; LVTTL

Input: Selection for receive

EQ = 1 (default) is for the 5-dB setting; EQ = 0 is for the 12-dB

EQ

23

equalization setting

setting.

Power Supply

VCC

8, 12, 19

Power

Power supply, 3.3 V ±5%

GND

11, 15, 20

Ground

The ground center pad of the package must be connected to

Thermal pad

Thermal pad

GND plane with thermal vias.

4

Input

Receiver input biasing voltage

2

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