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SM32C6711DGDPA16EP Datasheet(PDF) 7 Page - Texas Instruments |
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SM32C6711DGDPA16EP Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 128 page  SM320C6711EP, SM320C6711BEP, SM320C6711CEP, SM320C6711DEP FLOATINGPOINT DIGITAL SIGNAL PROCESSORS SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block and CPU (DSP core) diagram Test C6000 CPU (DSP Core) Data Path B B Register File Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Power-Down Logic .L1† .S1† .M1† .D1 .D2 .M2† .S2† .L2† 32 SDRAM ROM/FLASH SBSRAM I/O Devices L1P Cache Direct Mapped 4K Bytes Total Control Registers Control Logic L1D Cache 2-Way Set Associative 4K Bytes Total In-Circuit Emulation Interrupt Control Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs C6711/C6711B/C6711C/C6711D Digital Signal Processors † In addition to fixed-point instructions, these functional units execute floating-point instructions. ‡ The C6711C/C6711D device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider) and a PLL Controller which is different from the hardware PLL peripheral on the C6711 and C6711B devices. § Applicable to the C6711C/C6711D device only Enhanced DMA Controller (16 channel) 16 L2 Memory 4 Banks 64K Bytes Total PLL‡ Timer 0 External Memory Interface (EMIF) Multichannel Buffered Serial Port 1 (McBSP1) Multichannel Buffered Serial Port 0 (McBSP0) Host Port Interface (HPI) SRAM Timer 1 Boot Configuration Interrupt Selector GPIO§ |
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