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RM48L730PGET Datasheet(PDF) 1 Page - Texas Instruments |
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RM48L730PGET Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 147 page  RM48L930 RM48L730 RM48L530 www.ti.com SPNS176 – SEPTEMBER 2011 RM48Lx30 16/32-Bit RISC Flash Microcontroller 1 RM48Lx30 16/32-Bit RISC Flash Microcontroller 1.1 Features 1 • High-Performance Microcontroller for Safety • Multiple Communication Interfaces Critical Applications – USB – Dual CPU’s running in lockstep • 2-port USB Specification, revision – ECC on flash and RAM interfaces 2.0-compatible host controller, based on the OHCI Specification for USB, release – Built-In Self Test for CPU and on-chip RAMs 1.0 – Error Signaling Module with Error Pin • One full-speed USB device compatible – Voltage and Clock Monitoring with the USB Specification, revision 2.0 • ARM® Cortex™ – R4F 32-bit RISC CPU and USB Specification, revision 1.1 – Efficient 1.6DMIPS/MHz with 8-stage pipeline – Three CAN Controllers (DCAN) – Floating-Point Unit with Single/Double • 64 mailboxes with parity protection each Precision • Compliant to CAN protocol version 2.0B – 12-Region Memory Protection Unit – Inter-Integrated Circuit (I2C) – Open Architecture with 3rd Party Support – Three Multi-buffered Serial Peripheral • Operating Conditions Interfaces (MibSPI) – Up to 200MHz System Clock • 128 Words with Parity Protection each – Core Supply Voltage (VCC): 1.2V nominal – Two Standard Serial Peripheral Interfaces – I/O Supply Voltage (VCCIO): 3.3V nominal (SPI) • Integrated Memory – Local Interconnect Network Interface (LIN) – Up to 3MB Program Flash with ECC Controller – Up to 256KB RAM with ECC • Compliant to LIN protocol version 2.1 – 64KB Flash for emulated EEPROM – Standard Serial Communication Interface • 16- bit External Memory Interface (SCI) • Common Platform Architecture • Two High-End Timer Modules (N2HET) – Consistent memory map across family – N2HET1: 32 programmable channels – Real-Time Interrupt Timer (RTI) OS Timer – N2HET2: 20 programmable channels – 96-channel Vectored Interrupt Module (VIM) – 160 Word Instruction RAM with parity protection each – 2-channel Cyclic Redundancy Checker (CRC) – Each includes Hardware Angle Generator • Direct Memory Access (DMA) Controller – Dedicated Transfer Unit for each N2HET – 16 Channels and 32 Control Packets (HTU) – Parity protection for control packet RAM • Two 10/12-bit Multi-Buffered ADC Modules – DMA Accesses Protected by Dedicated MPU – ADC1: 24 channels • Frequency-Modulated Phase-Locked-Loop – ADC2: 16 channels (FMPLL) with Built-In Slip Detector – 16 shared channels • Separate Non-Modulating PLL – 64 result buffers with parity protection each • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components • Packages • JTAG Security Module – 144-pin Quad Flatpack (PGE) [Green] • Trace and Calibration Capabilities – 337-Ball Grid Array (ZWT) [Green] – Embedded Trace Macrocell (ETM-R4) – Data Modification Module (DMM) – RAM Trace Port (RTP) – Parameter Overlay Module (POM) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative Copyright © 2011, Texas Instruments Incorporated or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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