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ONET8501PBRGTR Datasheet(PDF) 9 Page - Texas Instruments |
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ONET8501PBRGTR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 27 page P S S P SDA SCK t BUF t LOW t r t f t HIGH t HDSTA t HDSTA t HDDAT t SUDAT t SUSTA t SUSTO S SDA SCK P 1-7 SLAVE ADDRESS R/W ACK 8 9 1-7 8 9 REGISTER ADDRESS ACK 1-7 8 9 ACK REGISTER FUNCTION ONET8501PB www.ti.com ....................................................................................................................................................................................................... SLLS910 – JULY 2008 Figure 3. I2C Timing Diagram Table 4. Timing Diagram Definitions PARAMETER MIN MAX UNIT fSCK SCK clock frequency 400 kHz tBUF Bus free time between START and STOP conditions 1.3 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 µs tLOW Low period of the SCK clock 1.3 µs tHIGH High period of the SCK clock 0.6 µs tSUSTA Setup time for a repeated START condition 0.6 µs tHDDAT Data HOLD time 0 µs tSUDAT Data setup time 100 ns tR Rise time of both SDA and SCK signals 300 ns tF Fall time of both SDA and SCK signals 300 ns tSUSTO Setup time for STOP condition 0.6 µs Figure 4. I2C Data Transfer Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :ONET8501PB |
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