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FAN54014 Datasheet(PDF) 31 Page - Fairchild Semiconductor |
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FAN54014 Datasheet(HTML) 31 Page - Fairchild Semiconductor |
31 / 37 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5401X Family • Rev. 1.0.2 31 Read and Write Transactions The figures below outline the sequences for data read and write. Bus control is signified by the shading of the packet, defined as Master Drives Bus and Slave Drives Bus . All addresses and data are MSB first. Table 21. Bit Definitions for Figure 49, Figure 50 Symbol Definition S START, see Figure 46. A ACK. The slave drives SDA to 0 to acknowledge the preceding packet. A NACK. The slave sends a 1 to NACK the preceding packet. R Repeated START, see Figure 48 P STOP, see Figure 47 S Slave Address A Reg Addr A A P 0 7 bits 8 bits 8 bits Data 000 Figure 49. Write Transaction S Slave Address A Reg Addr A 0 7 bits 8 bits R Slave Address 7 bits 1 A Data A 8 bits 00 0 1 P Figure 50. Read Transaction |
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