A2

0

1

S

0

0

A1 A0 0

A

A

Data From Register

Slave Address

Slave Address

R/W

ACK From

Slave

Command Byte

ACK From

Slave

S

A2

0

1

0

0

A1 A0

R/W

1 A

Data

A

ACK From

Master

Data

Data From Register

NACK From

Master

NA P

Last Byte

ACK From

Slave

SCL

SDA

INT

Start

Condition

R/W

Read From

Port

Data Into

Port

Stop

Condition

ACK From

Master

NACK From

Master

ACK From

Slave

Data From Port

Slave Address

Data From Port

1

9

8

7

6

5

4

3

2

A2

0

1

S

0

0

A1 A0 1

A

Data 1

Data 4

A

NA P

Data 2

Data 3

Data 4

Data 5

TCA9554

www.ti.com

SCPS233A – NOVEMBER 2011 – REVISED MARCH 2012

Reads

The bus master first must send the TCA9554 address with the least significant bit (LSB) set to a logic 0 (see

Figure 6 for device address). The command byte is sent after the address and determines which register is

accessed. After a restart, the device address is sent again, but this time the LSB is set to a logic 1. Data from the

register defined by the command byte then is sent by the TCA9554 (see Figure 10 and Figure 11). After a

restart, the value of the register defined by the command byte matches the register being accessed when the

restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation

on the number of data bytes received in one read transmission, but when the final byte is received, the bus

master must not acknowledge the data.

Figure 10. Read From Register

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A.

This figure assumes the command byte has previously been programmed with 00h.

B.

Transfer of data can be stopped at any moment by a Stop condition.

C.

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port. See Figure 10 for these details.

Figure 11. Read From Input Port Register

Copyright © 2011–2012, Texas Instruments Incorporated

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