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SRC4190-Q1 Datasheet(PDF) 20 Page - Texas Instruments |
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SRC4190-Q1 Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 29 page 
SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com Table 2 illustrates data format selection for the input port. The IFMT0 (pin 10), IFMT1 (pin 11), and IFMT2 (pin 12) inputs are utilized to set the input port data format. Table 2. Input Port Data Format Selection IFMT2 IFMT1 IFMT0 INPUT PORT DATA FORMAT 0 0 0 24-bit left justified 0 0 1 24-bit I2S 0 1 0 Unused 0 1 1 Unused 1 0 0 16-bit right justified 1 0 1 18-bit right justified 1 1 0 20-bit right justified 1 1 1 24-bit right justified Output Port Operation The audio output port is a four-wire synchronous serial interface that may operate in either slave or master mode. The SDOUT output (pin 23) is the serial audio data output. Audio data is output at this pin in one of four data formats: Philips I2S, left justified, right justified, or TDM. The audio data word length may be 16, 18, 20, or 24 bits. For all word lengths, the data is triangular PDF dithered from the internal 28-bit data path. The data formats (with the exception of TDM mode) are shown in Figure 6, while critical timing parameters are shown in Figure 7 and listed in the Electrical Characteristics table. The TDM format and timing are shown in Figure 11 and Figure 12, respectively, while examples of standard TDM configurations are shown in Figure 13 and Figure 14. The bit clock is either input or output at BCKO (pin 25). In slave mode, BCKO is configured as an input pin, and may operate at rates from 32fS to 128fS, with a minimum of one clock cycle for each data bit. The exception is the TDM mode, where the BCKO must operate at N × 64fS, where N is equal to the number of SRC4190 devices included on the TDM interface. In master mode, BCKO operates at a fixed rate of 64fS for all data formats except TDM, where BCKO operates at the reference clock (RCKI) frequency. Additional information regarding TDM mode operation is included in the Application Information section of this data sheet. The left/right word clock, LRCKO (pin 24), may be configured as an input or output pin. In slave mode, LRCKO is an input pin, while in master mode it is an output pin. In either case, the clock rate is equal to fS, the output sampling frequency. The clock duty cycle is fixed to 50% for I2S, left justified, and right justified formats in master mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode. 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 |
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