SN100KT5574

OCTAL ECLTOTTL TRANSLATOR WITH DTYPE

EDGETRIGGERED FLIPFLOPS AND 3STATE OUTPUTS

POST OFFICE BOX 655303

6

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

LOAD CIRCUIT

t

PHL

t

PLH

VOH

VOL

−950 mV

−1690 mV

50%

50%

Test Point

R1

R2

S1

CL

7 V

(See Note A)

Open

1.5 V1.5 V

−950 mV

TEST

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

S1

Open

Open

Open

Closed

Open

Closed

SWITCH POSITION TABLE

High-Level

Input

Low-Level

Input

tw

50%

50%

50%

50%

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V

3 V

0

Output

Control

(Low-Level

Enabling)

Output

Waveform 1

(See Note D)

Output

Waveform 2

(See Note D)

0

VOH

VOL

3.5 V

VOLTAGE WAVEFORMS

TTL ENABLE AND DISABLE TIMES

tPLZ

tPZL

tPZH

tPHZ

1.5 V

1.5 V

0.3 V

0.3 V

1.5 V

50%

50%

50%

−1690 mV

th

Timing

Input

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

ECL Input

(See Note C)

Out-of-Phase

TTL Output

VOLTAGE WAVEFORMS

ECL-INPUT PROPAGATION DELAY TIMES

tsu

80%

20%

80%

20%

tr

tf

VOH

VOL

1.5 V1.5 V

In-Phase

TTL Output

t

PLH

t

PHL

−950 mV

−1690 mV

80%

20%

tr

20%

tf

80%

50%

−950 mV

−1690 mV

−950 mV

−1690 mV

tf

tr

80%

20%

80%

20%

NOTES: A.CL includes probe and jig capacitance.

B. For TTL inputs, input pulses are supplied by generators having the following characteristics PRR

≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns,

tf ≤ 2.5 ns.

C. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, Zo = 50 Ω, tr ≤ 0.7 ns,

tf ≤ 0.7 ns.

D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

E. The outputs are measured one at a time with one transition per measurement.

figure 1. load circuit and voltage waveforms