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SN75LVCP601 Datasheet(PDF) 4 Page - Texas Instruments |
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SN75LVCP601 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 23 page 20 19 18 17 16 6 7 8 9 10 VCC EN DE 2 DE 1 DEW 2 EQ 2 EQ 1 VCC DEW 1 GND LVCP601RTJ Thermal Pad must be soldered to PCB GND plane for efficient thermal performance Bottom View DEW 2 DE 1 DE 2 EN VCC VCC DEW 1 EQ 2 EQ 1 GND LVCP601RTJ Top View 18 19 20 10 9 8 7 6 16 17 SN75LVCP601 SLLSE41B – JUNE 2010 – REVISED FEBRUARY 2012 www.ti.com PACKAGE PINOUT PIN FUNCTIONS PIN PIN TYPE DESCRIPTION NO. NAME HIGH-SPEED DIFFERENTIAL I/O 2 RX1N I, CML 1 RX1P I, CML Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an internal voltage bias by a dual-termination resistor circuit. 12 RX2N I, CML 11 RX2P I, CML 14 TX1N O, VML 15 TX1P O, VML Non-inverting and inverting VML differential output for CH 1 and CH 2. These pins are internally tied to voltage bias by termination resistors. 4 TX2N O, VML 5 TX2P O, VML CONTROL PINS 7 EN I, LVCMOS Device enable/disable pin, internally pulled to VCC. See Table 2. 8, 9 DE1, DE2(1) I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2 17, 19 EQ1, EQ2(1) I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2 16, 6 DEW1, DEW2 I, LVCMOS De-emphasis width control for CH 1 and CH 2. See Table 2. POWER 10, 20 Vcc Power Positive supply should be 3.3 V ± 10%. 3, 13, 18 GND Power Supply ground (1) Internally biased to Vcc/2 with >200-kΩ pullup/pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be <1 µA; otherwise, drive to Vcc/2 to assert mid-level state. 4 Copyright © 2010–2012, Texas Instruments Incorporated |
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