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MF10ACN Datasheet(PDF) 9 Page - Texas Instruments

Part No. MF10ACN
Description  Universal Monolithic Dual Switched Capacitor Filter
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

MF10ACN Datasheet(HTML) 9 Page - Texas Instruments

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Pin Descriptions
LP(1,20), BP(2,19), N/AP/HP(3,18)
The second order lowpass, bandpass
and
notch/allpass/highpass
outputs.
These outputs can typically sink 1.5 mA
and source 3 mA. Each output typically
swings to within 1V of each supply.
INV(4,17)
The inverting input of the summing
op-amp of each filter. These are high
impedance inputs, but the non-inverting
input is internally tied to AGND, making
INV
A and INVB behave like summing
junctions
(low
impedance,
current
inputs).
S1(5,16)
S1 is a signal input pin used in the
allpass filter configurations (see modes
4 and 5). The pin should be driven with
a source impedance of less than 1 k
Ω.
If S1 is not driven with a signal it should
be tied to AGND (mid-supply).
S
A/B(6)
This pin activates a switch that con-
nects one of the inputs of each filter’s
second summer to either AGND (S
A/B
tied to V
) or to the lowpass (LP) output
(S
A/B tied to V
+). This offers the flexibil-
ity needed for configuring the filter in its
various modes of operation.
V
A
+(7),V
D
+(8)
Analog positive supply and digital posi-
tive supply. These pins are internally
connected through the IC substrate and
therefore V
A
+ and V
D
+ should be de-
rived from the same power supply
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and by-
passed by a single capacitor.
V
A
(14), V
D
(13)
Analog and digital negative supplies.
The same comments as for V
A
+ and
V
D
+ apply here.
LSh(9)
Level shift pin; it accommodates vari-
ous clock levels with dual or single sup-
ply operation. With dual ±5V supplies,
the MF10 can be driven with CMOS
clock levels (±5V) and the LSh pin
should be tied to the system ground. If
the same supplies as above are used
but only TTL clock levels, derived from
0V to +5V supply, are available, the
LSh pin should be tied to the system
ground. For single supply operation (0V
and +10V) the V
A
,V
D
pins should be
connected to the system ground, the
AGND pin should be biased at +5V and
the LSh pin should also be tied to the
system ground for TTL clock levels.
LSh should be biased at +5V for CMOS
clock
levels
in
10V
single-supply
applications.
CLKA(10),
CLKB(11)
Clock inputs for each switched capaci-
tor filter building block. They should
both be of the same level (TTL or
CMOS). The level shift (LSh) pin de-
scription discusses how to accommo-
date their levels. The duty cycle of the
clock should be close to 50% especially
when clock frequencies above 200 kHz
are used. This allows the maximum
time for the internal op-amps to settle,
which yields optimum filter operation.
50/100/CL(12)
By
tying
this
pin
high
a
50:1
clock-to-filter-center-frequency ratio is
obtained. Tying this pin at mid-supplies
(i.e. analog ground with dual supplies)
allows the filter to operate at a 100:1
clock-to-center-frequency ratio. When
the pin is tied low (i.e., negative supply
with dual supplies), a simple current
limiting circuit is triggered to limit the
overall supply current down to about
2.5 mA. The filtering action is then
aborted.
AGND(15)
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or bi-
ased to mid-supply for single supply
operation. For a further discussion of
mid-supply biasing techniques see the
Applications Information (Section 3.2).
For
optimum
filter
performance
a
“clean” ground must be provided.
1.0 Definition of Terms
f
CLK: the frequency of the external clock signal applied to pin
10 or 11.
f
O: center frequency of the second order function complex
pole pair. f
O is measured at the bandpass outputs of the
MF10, and is the frequency of maximum bandpass gain.
(
Figure 1)
f
notch: the frequency of minimum (ideally zero) gain at the
notch outputs.
f
z: the center frequency of the second order complex zero
pair, if any. If f
z is different from fO and if QZ is high, it can be
observed as the frequency of a notch at the allpass output.
(
Figure 10)
Q: “quality factor” of the 2nd order filter. Q is measured at the
bandpass outputs of the MF10 and is equal to f
O divided by
the −3 dB bandwidth of the 2nd order bandpass filter (
Figure
1). The value of Q determines the shape of the 2nd order
filter responses as shown in
Figure 6.
Q
Z: the quality factor of the second order complex zero pair,
if any. Q
Z is related to the allpass characteristic, which is
written:
where Q
Z = Q for an all-pass response.
H
OBP: the gain (in V/V) of the bandpass output at f = fO.
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