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MF10ACN Datasheet(PDF) 26 Page - Texas Instruments

Part No. MF10ACN
Description  Universal Monolithic Dual Switched Capacitor Filter
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

MF10ACN Datasheet(HTML) 26 Page - Texas Instruments

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3.0 Applications Information
(Continued)
any of the outputs will cause gain nonlinearities and will
change f
O and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
f
CLK/fO significantly higher than the nominal value, especially
if Q is also high. An extreme example is a bandpass filter
having unity gain,aQof20, and f
CLK/fO = 250 with pin 12
tied to ground (100:1 nominal). R4/R2 will therefore be equal
to 6.25 and the offset voltage at the lowpass output will be
about +1V. Where necessary, the offset voltage can be
adjusted by using the circuit of
Figure 20. This allows adjust-
ment of V
OS1, which will have varying effects on the different
outputs as described in the above equations. Some outputs
cannot be adjusted this way in some modes, however
(V
OS(BP) in modes 1a and 3, for example).
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The MF10 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An
important characteristic of sampled-data systems is their
effect on signals at frequencies greater than one-half the
sampling frequency. (The MF10’s sampling frequency is the
same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be “reflected” to a
frequency less than one-half the sampling frequency. Thus,
an input signal whose frequency is f
s/2 + 100 Hz will cause
the system to respond as though the input frequency was
f
s/2 − 100 Hz. This phenomenon is known as “aliasing”, and
can be reduced or eliminated by limiting the input signal
spectrum to less than f
s/2. This may in some cases require
the use of a bandwidth-limiting filter ahead of the MF10 to
limit the input spectrum. However, since the clock frequency
is much higher than the center frequency, this will often not
be necessary.
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling pe-
riod, resulting in “steps” in the output voltage which occur at
the clock rate (
Figure 21). If necessary, these can be
“smoothed” with a simple R–C low-pass filter at the MF10
output.
The ratio of f
CLK to fC (normally either 50:1 or 100:1) will also
affect performance. A ratio of 100:1 will reduce any aliasing
problems and is usually recommended for wideband input
signals. In noise sensitive applications, however, a ratio of
50:1 may be better as it will result in 3 dB lower output noise.
The 50:1 ratio also results in lower DC offset voltages, as
discussed in Section 3.4.
The accuracy of the f
CLK/fO ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
“Typical Performance Characteristics”. As Q is changed, the
true value of the ratio changes as well. Unless the Q is low,
the error in f
CLK/fO will be small. If the error is too large for a
specific application, use a mode that allows adjustment of
the ratio with external resistors.
It should also be noted that the product of Q and f
Oshould be
limited to 300 kHz when f
O < 5 kHz, and to 200 kHz for fO >
5 kHz.
01039932
FIGURE 21. The Sampled-Data Output Waveform
www.national.com
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