SN74LVTH18502AEP, SN74LVTH182502AEP

3.3V ABT SCAN TEST DEVICES

WITH 18BIT UNIVERSAL BUS TRANSCEIVERS

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

1

POST OFFICE BOX 655303

− One Assembly/Test Site, One Fabrication

Site

Sources (DMS) Support

SCOPE

 Family of Testability Products

Widebus

 Family

Mixed-Mode Signal Operation (5-V Input

Down to 2.7 V

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Need for External Pullup Resistors

Device Have Equivalent 25-

Ω Series

Resistors, So No External Resistors Are

Required

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

− IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

− Parallel-Signature Analysis at Inputs

− Pseudorandom Pattern Generation From

Outputs

− Sample Inputs/Toggle Outputs

− Binary Count From Outputs

− Device Identification

− Even-Parity Opcodes

description/ordering information

The SN74LVTH18502A and SN74LVTH182502A scan test devices, with 18-bit universal bus transceivers, are

members of the Texas Instruments SCOPE

 testability integrated-circuit family. This family of devices supports

IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan

access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit

transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples

of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP

in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

LQFP − PM

Tape and reel

8V18502AIPMREP

LH18502AEP

−40

°C to 85°C

LQFP − PM

Tape and reel

8V182502AIPMREP§

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

§ Product Preview

Copyright

 2004, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

SCOPE, Widebus, and UBT are trademarks of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.