SN74LVTH273EP

3.3V ABT OCTAL DTYPE FLIPFLOP

WITH CLEAR

SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006

1

POST OFFICE BOX 655303

− One Assembly/Test Site, One Fabrication

Site

Sources (DMS) Support

(5-V Input and Output Voltages With

Down to 2.7 V

Operation

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

Need for External Pullup/Pulldown

Resistors

JESD 17

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

to provide a TTL interface to a 5-V system environment.

The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct clear (CLR) input. Information at the data

(D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of

the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition

time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal

has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74LVTH273IPWREP

LH273EP

−55

°C to 125°C

SOP − NS

Tape and reel

SN74LVTH273MNSREP

LVTH273EP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Copyright

 2006, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PW OR NS PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLR

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK