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SL74LV374 Datasheet(PDF) 1 Page - System Logic Semiconductor |
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SL74LV374 Datasheet(HTML) 1 Page - System Logic Semiconductor |
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SL74LV374 System Logic Semiconductor SLS OCTAL D-TIME FLIP-FLOP; POSITIVE EDGE- TRIGGER (3-StatE) SL74LV374 are compatible by pinning with SL74HC374 and SL74HCT374 series. Input voltage levels are compatible with standard CMOS levels. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS. • Supply voltage range from 2.0 to 3.2 V • LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • Output current 8 mÀ • Latch current value not less than 150 mÀ at Ò = 125 °Ñ • ESD acceptable values: not less than 2000 V as per HBM, and not less than 200 V as per MM ORDERING INFORMATION SL74LV374N Plastic DIP SL74LV374D SOIC TA = -40 ° to 125° C for all packages PIN ASSIGNMENT 374 OE 01 Q 0 02 D 0 03 D 1 04 Q 1 05 Q 2 06 D 2 07 D 3 08 Q 3 09 GND 10 20 19 18 17 16 15 14 13 12 11 D 7 D 6 Q 6 Q 5 D 5 D 4 Q 4 CP V CC Q 7 BLOCK DIAGRAM OE 01 Q 0 02 D 0 03 D 1 04 Q 1 05 Q 2 06 D 2 07 D 3 08 Q 3 09 19 18 17 16 15 14 13 12 11 D 7 D 6 Q 6 Q 5 D 5 D 4 Q 4 CP Q 7 Pin 20=VCC Pin 10 = GND FUNCTION TABLE Inputs Output OE CP Dn Qn L H H L L L L L, H, X no change H X X Z |
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