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SLWS131 Datasheet(PDF) 11 Page - Texas Instruments |
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SLWS131 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 37 page GRAYCHIP, INC. - 9 - JUNE 22, 1998 GC3021 MIXER AND CARRIER REMOVAL CHIP DATA SHEET This document contains information which may be changed at any time without notice 24 for initial acquisition and 31 for final tracking. The values of A and B are double buffered so that the loop bandwidth can be changed synchronous to an external sync signal. Initial acquisition can be greatly aided by presetting the PLL to an estimated frequency offset. This is done by loading the frequency register with the estimated frequency. In the mixer mode the PLL is turned off by clearing 2-A and 2-B, clearing the accumulator and setting the frequency register to the desired tuning frequency. The 32 bit frequency word is set to the desired frequency using the formula: , where “Frequency” is the desired frequency and “Clock Rate” is the chip’s clock rate. The frequency register is double buffered so that frequency changes can be made synchronous to external sync signals. The upper 16 bits of the current phase increment is monitored by the phase increment register. The register tracks the current phase increment when the “hold” control is low and holds the last value when “hold” is high. The user may wish to monitor the phase increment in order to reinitialize the PLL after a loss of signal, or to determine when carrier lock has been achieved. 2.9 NCO The PLL circuit generates a phase increment word which is used by the NCO to generate a sine/cosine sequence at the desired tuning frequency. The NCO circuit accumulates the phase and uses the upper 13 bits of the 32 bit accumulator to lookup 12 bit sines and cosines. A block diagram of the NCO circuit is shown in Figure 8. Figure 8. NCO CIRCUIT The accumulator output plus one half the phase increment is used in the high speed mode1 to look up the BCOS and BSIN values. This generates the proper “odd time” sine/cosine values needed in the high speed mode. The tuning range in the high speed mode is limited to +/- FIN/4, where FIN is thehigh speed input data rate. To tune to frequencies above FIN/4, the user must negate the odd-time output samples (both I and Q). This mixes the output down by FIN/2. For example, to mix down the frequency 0.3IN, the user should set the tuning frequency to +0.2FIN, and then negate the odd-time output data to give a final tuning of (0.2FIN - 0.5FIN) = -0.3FIN. 1. The high speed mode is the double rate real input mode, see Section 2.4 FREQ Frequency Clock Rate -----------------------------2 32 = 32 BIT PHASE ACCUMULATOR NCO Sync PHASE INCREMENT DIVIDE BY 2 Clear Dither Sync High Speed Mode TRIG TABLE ACOS ASIN 13 Bits 17 Bits 17 Bits 12 Bits 12 Bits TRIG TABLE BCOS BSIN 13 Bits 12 Bits 12 Bits Negate Sine CIN |
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