I

=

CHOP

V

REFX

5

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DRV8824

www.ti.com

SLVSA06E

– OCTOBER 2009 – REVISED AUGUST 2011

Current Regulation

The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current

chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage

and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the

current until the beginning of the next PWM cycle.

In stepping motors, current regulation is used to vary the current in the two windings in a semi-sinusoidal fashion

to provide smooth motion.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor

connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input

from the xVREF pins.

The full-scale (100%) chopping current is calculated in Equation 1.

(1)

Example:

If a 0.5-

Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be

3.3 V / (5 x 0.5

Ω) = 1.32 A.

The reference voltage is scaled by an internal DAC that allows fractional stepping of a bipolar stepper motor, as

described in the microstepping indexer section below.

Decay Mode

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM

current chopping threshold is reached. This is shown in Figure 3 as case 1. The current flow direction shown

indicates positive current flow.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or

slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to

allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is

disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 3 as case 2.

In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is

shown in Figure 3 as case 3.

Figure 3. Decay Mode

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© 2009–2011, Texas Instruments Incorporated

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