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DRV3201QPAPQ1 Datasheet(PDF) 10 Page - Texas Instruments |
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DRV3201QPAPQ1 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 44 page  DRV3201-Q1 SLVSBD6 – MAY 2012 www.ti.com PIN FUNCTIONS (continued) PIN TYPE(1) DESCRIPTION NAME NO. GNDA 11 GND Analog ground SCTH 12 HVI_A Short circuit threshold, reference input voltage for VDS monitoring. SLS1 13 PWR Source low-side 1, connected to external power MOSFET for gate discharge and VDS monitoring. GLS1 14 PWR Gate low-side 1, connected to gate of external power MOSFET. SHS1 15 PWR Source high-side 1, connected to external power MOS transistor for gate discharge and VDS monitoring. GHS1 16 PWR Gate high-side 1, connected to gate of external power MOS transistor. PH1C 17 LVO_D Phase comparator output1 PH2C 18 LVO_D Phase comparator output2 PH3C 19 LVO_D Phase comparator output3 GNDA 20 GND Analog ground DRVOFF 21 HVI_D Driver OFF (high active), secondary bridge driver disable SCLK 22 HVI_D SPI clock GNDL 23 GND Logic ground NCS 24 HVI_D SPI chip select SDI 25 HVI_D SPI data input SDO 26 LVO_D SPI data output GNDA 27 GND Analog ground VS 28 Supply Power supply voltage BOOST 29 Supply Boost output voltage, used as supply for the gate-drivers. SW 30 PWR Boost converter switching node connected to external coil and external diode. GNDLS_B 31 GND Boost GND to set current limit. Boost switching current goes through this pin via exterior resistor to GND. NC 32 NC NC pin, connected to GND during normal application. NC 33 NC NC pin, connected to GND during normal application. B_EN 34 HVI_D Boost enable. Enable boost operation or disable during e.g. sensitive measurement. CSM 35 HVI_D Configurable safety mode (high active), defines the level of safety. EN 36 HVI_D Enable (high active) of the device RSTN 37 HVI_D Reset (low active) ERR 38 LVO_D Error (low active). Error pin to indicate detected error. GNDA 39 GND Ground analog VCC5 40 LVO_A VCC5 regulator, for internal use only. Recommended external decoupling capacitance: 4.7 nF. External load < 100 µA TEST 41 HVI_A TEST mode input, connected to GND during normal application. VCC3 42 LVO_A VCC3 regulator, for internal use only. Recommended external decoupling capacitance: 4.7 nF. External load < 100 µA AMUX 43 LVO_A Analog TEST output MUX, connected to GND during normal application. (GND) ADREF 44 LVI_A ADC reference of MCU, used as maximum voltage clamp for O1-O4. GNDL 45 GND Logic ground O4 46 LVO_A Output second stage current sense amplifier 2 O3 47 LVO_A Output second stage current sense amplifier 1 O2 48 LVO_AO Output first stage current sense amplifier 2 IN2 49 HVI_A Current sense input N 2 IP2 50 HVI_A Current sense input P 2 GNDA 51 GND Ground analog RO 52 LVO_A Current sense reference output for the shift voltage. RI 53 HVI_A Current sense reference input for the shift voltage. 10 Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV3201-Q1 |
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