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SL74HCT273 Datasheet(PDF) 4 Page - System Logic Semiconductor

Part No. SL74HCT273
Description  Octal D Flip-Flop with Common Clock and Reset(High-Performance Silicon-Gate CMOS)
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Maker  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
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SL74HCT273 Datasheet(HTML) 4 Page - System Logic Semiconductor

   
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SL74HCT273
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(V
CC =5.0 V
± 10%, C
L=50pF,Input t r=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C to
-55
°C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
25
28
35
ns
tPHL
Maximum Propagation Delay , Reset to Q (Figures
2 and 4)
25
28
35
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
18
20
22
ns
CIN
Maximum Input Capacitance
10
10
10
pF
Power Dis sipation Capacitance (Per Gate)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC
2f+I
CCVCC
30
pF
TIMING REQUIREMENTS (V
CC =5.0 V
± 10%, C
L=50pF,Input t r=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tSU
Minimum Setup Time, Data to
Clock (Figure 3)
10
12
15
ns
th
Minimum Hold Time, Clock to
Data (Figure 3)
3.0
3.0
3.0
ns
trec
Minimum Recovery Time,
Reset Inactive to Clock (Figure
2)
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
12
15
18
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
12
15
18
ns
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
500
500
500
ns


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