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CLC-DRCS7-PCASM Datasheet(PDF) 7 Page - Texas Instruments |
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CLC-DRCS7-PCASM Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 38 page  Rev. 2.01 January 25, 2001 6 ©2001 National Semiconductor Corporation The nominal component values for the filter provide a cen- ter frequency of 150MHz, a 3dB bandwidth of 18MHz, and an insertion loss of 0.7dB. Assuming an ADC sample rate of 52MSPS, the filter provides about 4dB of attenua- tion at the closest image frequency which is at 162MHz (Figure 8). More attenuation is possible by increasing the Q of the filter, but this would make the center frequency tolerance more critical and increase the group delay through the filter (the stability of the AGC loop is reduced by large group delays). More attenuation will also be achieved if the IF is moved further away from 156MHz. To change the IF frequency of the DRCS7 Board, the noise filter components must be changed. The equations below pertain to Figure 9 and provide a means of comput- ing the new values: EQ. 4 EQ. 5 EQ. 6 EQ. 7 In these equations, , , is the filter gain at , and is the quality factor of the inductor at . In addition to setting the center frequency of the filter, capacitors and absorb the transient current that is sourced out of the ADC coincident with the sampling instant. It is recommended that and be no less than 20pF. It is easy to calculate a new set of filter components using a spreadsheet program set up as follows: Start by selecting an inductor with a relatively high Q (30- 40). Next, iteratively try available capacitor values for and . Use to fine-tune the result. This example uses 20pF and 1pF capacitors with a 33nH inductor for a center frequency of 247.9MHz. Once the final PCB is available the center frequency should be checked to verify the effects of PCB parasitics. The frequency response of the noise filter can be checked at spot frequencies by observing either the CLC5902 Mixer AI or BI outputs in debug mode with the NCO set to 0 frequency and 0 phase. The tuning can be verified at the CLC5902 output by sweeping both the input frequency and the CLC5902 tuning so that they track. The test signal must be input after the IF SAW to use this method. 4dB 150 156 162 Frequency (MHz) Sampling Image IF Frequency 3X Sampling Frequency Baseband Filter Baseband Filter Translated To Sampling Images LC Noise Filter Figure 8 Illustration of the need for noise filter attenuation at the sampling images. 202 208 214 4X Sampling Frequency The desired signal at 150MHz appears as a 6MHz signal at the ADC output. The other sampling images at 162MHz, 202MHz, 214MHz, ... will also appear as 6MHz signals at the ADC output. The LC noise filter prevents extra noise from these sampling images from appearing at the ADC output. 6MHz ω c 1 L 1CT ----------------- = ω BW 1 R TCT ------------- = G LC 1 R T Q L ------- C T L 1 ------ ⋅ + = C T C 93 2 ⁄ C 99 1.5pF ++ = C 93 C 94 = R T 600 || 1K = 375 Ω = G LC ω c Q L ω c C 93 C 94 C 93 C 94 Figure 9 Noise filter components for AIN1. L1 C93 C94 1.5p 1K 600 C99 DVGA Output ADC Input and Stray PCB Capacitance C93, C94 0.00000000002 C99 0.000000000001 Parasitic 0.0000000000015 Ct =B1/2+B2+B3 L1 0.000000033 Fcenter =1/(2*3.14*(B7*B5)^0.5) A B 1 2 3 4 5 6 7 8 9 C 93 C 94 C 99 |
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Similar Description - CLC-DRCS7-PCASM |
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