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CLC-DRCS7-PCASM Datasheet(PDF) 6 Page - Texas Instruments |
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CLC-DRCS7-PCASM Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 38 page  ©2001 National Semiconductor Corporation 5 Rev. 2.01 January 25, 2001 Note The trace from pin 2 to pin 4 of U12 must be cut when U12 is used. The default serial output configuration is compatible with the TI TMS320C54X serial input. To interface to the ‘C54X, set the DSP serial port in continuous mode (FSM bit set to 0) with frame ignore enabled (FIG bit set to 1). In this mode the 24-bit words may be read as 3 groups of 8 bits. The overall input stream of four 24-bit words is read as twelve 8-bit words for later reassembly by the DSP. Additional serial port modes are discussed in the CLC5902 datasheet. CLC5902 Parallel Output The CLC5902 parallel output port is available on J1. It is a 16-bit port which can be mapped into the address space of a DSP. Each output component (AI, AQ, BI, & BQ) is allocated 2 registers of 16 bits. In 8-bit or 16-bit mode only a single register for each component needs to be read. To access the data place the proper address on the three 3287B6(/ lines and enable the outputs with 3287B(1. The 5'< signal can be used as an interrupt to indicate new data is ready. Complete details are provided in the CLC5902 datasheet. To facilitate testing of the parallel outputs SW1 can be used to force the state of 3287B6(/ and 3287B(1. Note All DRCS7 Board SW1 positions must be ‘OFF’ if the Data Capture Board is used for parallel data capture. CLC5902 Debug Output In some cases it may be desirable to look at signals inter- nal to the CLC5902. The CLC5902 debug port is tied to an internal 20-bit bus which can tap into the internal nodes shown in Figure 7. When in debug mode the DSP serial port pins are reconfigured and the serial port is no longer functional. 6&. is used to clock out the debug data at the proper rate. Additional information on the debug port is provided in the CLC5902 datasheet. The debug port can be used to observe the ADC outputs prior to processing by the CLC5902. This can be done by selecting the mixer output tap for the I component and set- ting the NCO frequency to zero. This setup is included in the default COP8 options. COP8 RS-232 Serial Interface The CLC5902 can be set to several default configurations by the COP8 micro-controller. To support more flexibility in evaluation the CLC5902 may also be completely recon- figured via an RS-232 serial port. The DRCS Control Panel software running on a PC sends commands to the COP8 serial port. The COP8 interprets these commands and programs the CLC5902 registers as required. DRCS7 Block Interfaces DVGA to ADC Interface (LC Noise Filter) While the IF SAW filter allows only the desired signal to be sampled, the DVGA introduces broad-band noise at the ADC input. A simple noise filter between the DVGA and ADC removes this noise. Failure to attenuate noise from the DVGA appearing at the ADC sampling image frequen- cies will degrade the system performance. Figure 8 shows the response of the noise filter with respect to the sampling images. 6&.B32/ = 5'<B32/ = 6)6B32/ = 0 tSFSV + tAND_DELAY + tDSP_SETUP ≤ 19.2ns 5'< 6)6 6&. 6)6 5'< 38.4ns &. = 52MHz, 6&. = &./2 tSFSV tSFSV tDSP_SETUP tAND_DELAY 19.2ns tSFSV = 7ns max from CLC5902 datasheet Figure 6 CLC5902 Serial Port Timing Figure 7 CLC5902 Debug Port Access Taps COS SIN NCO Input Mux I Q Mixer AI NCO Sin A NCO Cos A F1 Out AI AGC Shifter CIC & Scale FIR F1 FIR F1 GAIN F1 In AI Each channel is identical. For each channel the I & Q paths are identical. The debug tap is always aligned into the MSB of the 20-bit debug port output. |
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