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SL74HCT132 Datasheet(PDF) 3 Page - System Logic Semiconductor

Part No. SL74HCT132
Description  Quad 2-Input NAND Gate with Schmitt-Trigger Inputs(High-Performance Silicon-Gate CMOS)
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Manufacturer  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HCT132 Datasheet(HTML) 3 Page - System Logic Semiconductor

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SL74HCT132
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
°C
to
-55
°C
≤85
°C
≤125
°C
Unit
VT+max
Maximum Positive-
Going Input Threshold
Voltage
VOUT=0.1 V
I
OUT
≤ 20 µA
4.5
5.5
1.9
2.1
1.9
2.1
1.9
2.1
V
VT+min
Minimum Positive-
Going Input Threshold
Voltage
VOUT=0.1 V
I
OUT
 ≤ 20 µA
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
V
VT-max
Maximum Negative-
Going Input Threshold
Voltage
VOUT=VCC-0.1 V
I
OUT
≤ 20 µA
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
V
VT-min
Minimum Negative-
Going Input Threshold
Voltage
VOUT=VCC-0.1 V
I
OUT
 ≤ 20 µA
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
V
VHmax
Note
Maximum Hysteresis
Voltage
VOUT=0.1 V or VCC-0.1 V
I
OUT
 ≤ 20 µA
4.5
5.5
1.4
1.5
1.4
1.5
1.4
1.5
V
VHmin
Note
Minimum Hysteresis
Voltage
VOUT=0.1 V or VCC-0.1 V
I
OUT
 ≤ 20 µA
4.5
5.5
0.4
0.4
0.4
0.4
0.4
0.4
V
VOH
Minimum High-Level
Output Voltage
VIN
≤V
T-min or VT+max
I
out
 ≤ 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN
≤V
T-min or VT+max
I
OUT
 ≤ 4.0 mA
I
OUT
 ≤ 5.2 mA
4.5
3.98
3.84
3.7
VOL
Maximum Low-Level
Output Voltage
VIN
≥V
T+max
I
OUT
 ≤ 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN
≥ V
T+max
I
OUT
 ≤ 4.0 mA
I
OUT
 ≤ 5.2 mA
4.5
0.26
0.33
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0
µA
5.5
1.0
10
40
µA
∆I
CC
Additional Quiescent
Supply Current
VIN = 2.4 V, Any One Input
VIN=VCC or GND, Other
Inputs
≥-55°C
25
°C to
125
°C
mA
IOUT=0
µA
5.5
2.9
2.4
Note. VHmin>(VT+min)-(VT-max); VHmax=(VT+max)+(VT-min).


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