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bq24273

www.ti.com

SLUSB08 – JUNE 2012

APPLICATION INFORMATION

OUTPUT INDUCTOR AND CAPACITOR SELECTION GUIDELINES

When selecting an inductor, several attributes must be examined to find the right part for the application. First,

the inductance value should be selected. The bq24273 is designed to work with 1.5µH to 2.2µH inductors. The

chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some

efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may

not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.

Once the inductance has been selected, the peak current must be calculated in order to choose the current

rating of the inductor. Use equation 2 to calculate the peak current.

(5)

high currents possible with the bq24273, a thermal analysis must also be done for the inductor. Many inductors

have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the

ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty

cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of

the time, a

Δ40°C temperature rise current must be greater than 1.7A:

(6)

The bq24273 provides internal loop compensation. Using this scheme, the bq24273 is stable with 10µF to 200µF

of local capacitance. The capacitance on the BAT rail can be higher if distributed amongst the rail. To reduce the

output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is recommended for

local bypass to CS+.

PCB LAYOUT GUIDELINES

It is important to pay special attention to the PCB layout. The following provides some guidelines:

•

To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be

placed as close as possible to the bq24273

•

Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current

loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND

and PGND pins as possible to minimize the ground difference between the input and PMID_.

•

The local bypass capacitor from CS+ to GND should be connected between the CS+ pin and PGND of the

IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the

PGND pin.

•

Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place

components such that routing interrupts power stage currents). All small control signals should be routed

away from the high current paths.

•

The PCB should have a ground plane (return) connected directly to the return of all components through vias

(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is

also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is

typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-

coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small

layout and a single ground plane, there is no ground-bounce issue, and having the components segregated

minimizes coupling between signals.

•

The high-current charge paths into IN, BAT, CS+ and from the SW pins must be sized appropriately for the

maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be

connected to the ground plane to return current through the internal low-side FET.

•

For high-current applications, the balls for the power paths should be connected to as much copper in the

board as possible. This allows better thermal performance as the board pulls heat away from the IC.

Copyright © 2012, Texas Instruments Incorporated

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