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AFE7222IRGC25 Datasheet(PDF) 15 Page - Texas Instruments |
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AFE7222IRGC25 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 106 page  AFE7222 AFE7225 www.ti.com SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012 3.11 TIMING REQUIREMENTS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, unless otherwise noted. AFE7222 AFE7225 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX SCLK INPUT tSCLK CLOCK period 25 25 ns tSCLKH CLOCK pulse width high 12.5 12.5 ns Assuming 50/50 duty cycle tSCLKL CLOCK pulse width low 12.5 12.5 ns 3.12 TIMING REQUIREMENTS FOR RECEIVE PATH – LVDS AND CMOS MODES Typical values are at 25°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V, DVDD18_DAC = 1.8 V, DVDD18 = 1.8 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 Vpp clock amplitude, CLOAD = 5 pF (1), R LOAD = 100 Ω (2), unless otherwise noted. Min and max values are across the full temperature range T MIN = - 40°C to TMAX = 85°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V, DVDD18_DAC = 1.8 V, DVDD18 = 1.7 V to 1.9 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA Aperture delay 2 ns Aperture delay matching Between two channels on the same device ±120 ps Aperture delay matching Between two devices at same temperature and DVDD18 supply ±450 ps Jitter added by internal clock distribution, specified as it relates TJ Aperture jitter 250 fs rms to the receive ADC Default Mode 16 Mixer Enabled (RX_MIXER_EN = 1) 33 clock ADC Latency(3) cycles RX QMC Gain Phase Correction Enabled 22 (RX_QMC_CORR_ENA=1, RX_QMC_CORR_ENB=1) LVDS OUTPUT INTERFACE 2-WIRE MODE, DDR CLOCK(4), Sampling frequency = 125MSPS tsu Data setup time (5) Data valid(5) to zero-crossing of CLKOUTP 0.29 0.42 ns th Data hold time (5) Zero-crossing of CLKOUTP to data becoming invalid (5) 0.3 0.47 ns tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge tPDI = tDELAY ns cross-over 10 MSPS ≤ Sampling frequency ≤ 125 MSPS Ts = tdelay 11.5 13.8 15.5 ns 1/Sampling frequency Variation of tdelay Between two devices at same temperature and DVDD18 supply ±300 ps Duty cycle of differential clock, (ADC_DCLKOUTP- LVDS bit clock duty cycle ADC_DCLKOUTM) 10 MSPS ≤ Sampling frequency ≤ 125 50% MSPS 2-WIRE MODE, SDR CLOCK(4), Sampling frequency = 65MSPS tsu Data setup time (5) Data valid (5) to zero-crossing of CLKOUTP 0.85 1.08 ns th Data hold time (5) Zero-crossing of CLKOUTP to data becoming invalid (5) 1.08 1.21 ns Input clock rising edge cross-over to output clock rising edge tPDI Clock propagation delay cross-over 10 MSPS ≤ Sampling frequency ≤ 65 MSPS Ts = tPDI = 0.5*Ts + tDELAY ns 1/Sampling frequency tdelay 11.5 14 16.5 ns Variation of tdelay Between two devices at same temperature and DVDD18 supply ±300 ps Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 10 LVDS bit clock duty cycle 50% MSPS ≤ Sampling frequency ≤ 65 MSPS 1-WIRE MODE (DDR CLOCK ONLY)(4), Sampling frequency = 65MSPS tsu Data setup time (5) Data valid (5) to zero-crossing of CLKOUTP 0.25 0.39 ns (1) CLOAD is the effective external single-ended load capacitance between each output pin and ground (2) RLOAD is the differential load resistance between the LVDS output pair. (3) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (4) Measurements are done with a transmission line of 100- Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (5) Data valid refers to LOGIC HIGH of +100.0 mV and LOGIC LOW of -100.0 mV. Copyright © 2011–2012, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 15 Submit Documentation Feedback Product Folder Link(s): AFE7222 AFE7225 |
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