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AFE7225 Datasheet(PDF) 16 Page - Texas Instruments |
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AFE7225 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 106 page  AFE7222 AFE7225 SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com Typical values are at 25°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V, DVDD18_DAC = 1.8 V, DVDD18 = 1.8 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 Vpp clock amplitude, CLOAD = 5 pF (1), R LOAD = 100 Ω (2), unless otherwise noted. Min and max values are across the full temperature range T MIN = - 40°C to TMAX = 85°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V, DVDD18_DAC = 1.8 V, DVDD18 = 1.7 V to 1.9 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT th Data hold time (5) Zero-crossing of CLKOUTP to data becoming invalid (5) 0.26 0.4 ns Input clock rising edge cross-over to output clock rising edge tPDI Clock propagation delay cross-over 10 MSPS ≤ Sampling frequency ≤ 65 MSPS Ts = tPDI = 0.5*Ts + tDELAY ns 1/Sampling frequency tdelay 11.5 13.5 15.5 ns Variation of tdelay Between two devices at same temperature and DVDD18 supply ±300 ps Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 10 LVDS bit clock duty cycle 50% MSPS ≤ Sampling frequency ≤ 65 MSPS COMMON Rise time measured from -100 mV to +100 mV Fall time tRISE, Data rise time, Data fall measured from +100 mV to -100 mV 10 MSPS ≤ Sampling 0.08 ns tFALL time frequency ≤ 125 MSPS Rise time measured from -100 mV to +100 mV Fall time tCLKRISE, Output clock rise time, measured from +100 mV to -100 mV 10 MSPS ≤ Sampling 0.1 ns tCLKFALL Output clock fall time frequency ≤ 125 MSPS CMOS OUTPUT INTERFACE (6), Sampling frequency = 105MSPS(7) tsu Data setup time (8) Data valid to cross-over of ADC_DCLKOUT (8) 0.5 1.4 ns th Data hold time (8) Cross-over of ADC_DCLKOUT to data becoming invalid (8) 1.4 1.8 ns Input clock rising edge cross-over to output clock rising edge tPDI Clock propagation delay cross-over 10 MSPS ≤ Sampling frequency ≤ 105 MSPS Ts = tPDI = 0.5*Ts + tDELAY ns 1/Sampling frequency tdelay 14 16.5 19 ns Variation of tdelay Between two devices at same temperature and DVDD18 supply ±350 ps Duty cycle of output clock, ADC_DCLKOUT 10 MSPS ≤ Output clock duty cycle 46% Sampling frequency ≤ 105 MSPS Rise time measured from 20% to 80% of DVDD18 Fall time tRISE, Data rise time, Data fall measured from 80% to 20% of DVDD18 1 ≤ Sampling 0.76 ns tFALL time frequency ≤ 105 MSPS Rise time measured from 20% to 80% of DVDD18 Fall time tCLKRISE, Output clock rise time, measured from 80% to 20% of DRVDD 1 ≤ Sampling frequency 0.74 ns tCLKFALL Output clock fall time ≤ 105 MSPS (6) For Fs > 105 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (ADC_DCLKOUT). (7) For Fs > 65MSPS, CMOS output buffers strength is increased by writing serial register bits STR_CTRL<1:0> = '10'. (8) Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V. 16 ELECTRICAL SPECIFICATIONS Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE7222 AFE7225 |
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