HC573 datasheet(4/5 Pages) SLS

Part #	HC573

Description	Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)

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Manufacturer	SLS [System Logic Semiconductor]

Direct Link	http://www.slsemicon.co.kr/e_index.htm

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4 / 5 page

SL74HC573

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

tPLH, tPHL

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tPLH, tPHL

Maximum Propagation Delay,Latch Enable

to Q (Figures 2 and 5)

2.0

4.5

6.0

160

32

27

200

40

34

240

48

41

ns

tPLZ, tPHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tPZH, tPZL

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

CIN

Maximum Input Capacitance

-

10

pF

COUT

Maximum Three-State Output Capacitance

(Output in High-Impedance State)

-

15

pF

Power Dissipation Capacitance (Per Enabled

Output)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption: PD=CPDVCC

2f+I

CCVCC

23

pF

TIMING REQUIREMENTS (C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Input D

to Latch Enable

(Figure 4)

2.0

4.5

6.0

50

10

9

65

13

11

75

15

13

ns

th

Minimum Hold Time, Latch

Enable to Input D

(Figure 4)

2.0

4.5

6.0

5

ns

tw

Minimum Pulse Width, Latch

Enable (Figure 2)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

ns

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