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SL74HC597 Datasheet(PDF) 6 Page - System Logic Semiconductor

Part No. SL74HC597
Description  8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch(High-Performance Silicon-Gate CMOS)
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Maker  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
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SL74HC597 Datasheet(HTML) 6 Page - System Logic Semiconductor

   
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SL74HC597
System Logic
Semiconductor
SLS
FUNCTION TABLE
Inputs
Resulting Function
Operation
Reset
SerialShift/
ParallelLoad
Latch
Clock
Shift
Clock
Serial
Input
SA
Parallel
Inputs
A-H
Latch
Contents
Shift
Register
Contents
Output QH
Reset shift register
L
X
L,H,
X
X
X
U
L
L
Reset shift register;
load parallel data
into data latch
L
X
X
X
a-h
a-h
L
L
Load parallel data
into data latch
H
H
L,H,
X
a-h
a-h
U
U
Transfer latch
contents to shift
register
H
L
L,H,
X
X
X
U
LRN SRN
LRH
Contents of data
latch and shift
register are
unchanged
H
H
L,H,
L,H,
X
X
U
U
U
Load parallel data
into data latch and
shift register
H
L
X
X
a-h
a-h
a-h
h
Shift serial data into
shift register
H
H
X
D
X
*
SRA=D;
SRN SRN+1
SRG SRH
Load parallel data
into data latch and
shift serial data into
shift register
H
H
D
a-h
a-h
SRA=D;
SRN SRN+1
SRG SRH
SR = shift register contents
X = don’t care
LR = latch register contents
a-h = data at parallel data inputs A-H
D = data (L,H) at serial data input SA
* = depends on Latch Clock input
U = remains unchanged
INPUTS:
A, B, C, D, E, F, G, H - Parallel data inputs. Data on
these inputs is stored in the input latch on the rising
edge of the Latch Clock input.
SA - Serial data input. Data on this input is shifted into
the shift register on the rising edge of the Shift Clock
input if Serial Shift/Parallel Load is high. Data on this
input is ignored when Serial Shift/
Parallel Load is low.
SERIAL SHIFT/PARALLEL LOAD - Shift register
mode control. When a high level is applied to this pin,
the shift register is allowed to serially shift data. When
a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial
shifting is inhibited.
RESET - Asynchronous, Active-low shift register
reset. A low level applied to this input resets the shift
register to a low level, but does not change the data in
the input latch.
SHIFT CLOCK - Serial shift register clock. A low-to-
high transition on this input shifts data on the Serial
Data Input into the shift register and data in stage H is
shifted out QH, being replaced by the data previously
stored in stage G.
LATCH CLOCK - A low-to-high transition on this
input loads the parallel data on inputs A -H into the
input latch.
OUTPUT:
QH - Serial data output. This pin is the output from the
last stage of the shift register.


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