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SL74HC597 Datasheet(PDF) 4 Page - System Logic Semiconductor

Part No. SL74HC597
Description  8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch(High-Performance Silicon-Gate CMOS)
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Maker  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
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SL74HC597 Datasheet(HTML) 4 Page - System Logic Semiconductor

   
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SL74HC597
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
fmax
Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL
Maximum Propagation Delay, Latch Clock to QH
(Figures 1 and 8)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
tPLH, tPHL
Maximum Propagation Delay , Shift Clock to QH
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay , Reset to QH
(Figures 3 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH, tPHL
Maximum Propagation Delay, Serial Shift/
Parallel Load to QH (Figures 4 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC
2f+I
CCVCC
50
pF


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